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| 38c8 group description the 38c8 group is the 8-bit microcomputer based on the 740 family core technology. the 38c8 group has a lcd drive control circuit (bias control, time sharing control), a 10-bit a-d converter, and a serial i/o as additional functions. the various microcomputers in the 38c8 group include variations of internal memory size and packaging. for details, refer to the section on part numbering. features basic machine-language instructions ....................................... 71 the minimum instruction execution time ............................ 0.5 s (at 8 mhz oscillation frequency) memory size rom ............................................................................ 60 k bytes ram ............................................................................ 2048 bytes programmable input/output ports ............................................. 35 software pull-up resistors .................................................................. ports p0Cp3, p4 1 Cp4 7 interrupts ................................................... 15 sources, 15 vectors (includes key input interrupt) timers ............................................................ 8-bit ? 3, 16-bit ? 2 serial i/o ........................ 8-bit ? 1 (uart or clock-synchronized) a-d converter (32 khz operating available) ... 10-bit ? 8 channels lcd drive control circuit bias ................................................................................... 1/5, 1/7 duty .............................................................................. 1/16, 1/32 common output ............................................................... 16 or 32 segment output ............................................................... 52 or 68 main clock generating circuit (rc oscillation selectable) ...................... (connect to external ceramic resonator or resistor) sub-clock generating circuit ............................................. (connect to quartz-crystal oscilaltor) power source voltage in high-speed mode .................................................... 4.0 to 5.5 v in middle-speed mode ................................................ 2.2 to 5.5 v in low-speed mode ..................................................... 2.2 to 5.5 v power dissipation in high-speed mode ........................................................... 30 mw (at 8 mhz oscillation frequency, at 5 v power source voltage) in low-speed mode ............................................................. 60 w (at 32 khz oscillation frequency, at 3 v power source voltage, at wit state, at voltage multiplier operating, lcd drive waveform generating state) operating temperature range ................................... C 20 to 85c applications dot-matrix-type displays mitsubishi microcomputers single-chip 8-bit cmos microcomputer preliminar y notice: this is not a final specification. some parametric limits are subject to change.
2 single-chip 8-bit cmos microcomputer mitsubishi microcomputers 38c8 group preliminar y notice: this is not a final specification. some parametric limits are subject to change. pin configuration (top view) package type : 144p6q-a fig. 1 m38c89mf-xxxfp pin configuration 1 0 8 1 0 7 1 0 6 1 0 5 1 0 4 1 0 3 1 0 2 1 0 1 1 0 0 9 9 9 8 9 7 9 6 9 5 9 4 9 3 9 2 9 1 9 0 8 9 8 8 8 7 8 6 8 5 8 4 8 3 8 2 8 1 8 0 7 9 7 8 7 7 7 6 7 5 7 4 7 3 1 4 4 1 4 3 1 4 2 1 4 1 1 4 0 135 1 3 9 1 3 8 1 3 7 1 3 6 134 133 132 131 130 129 128 1 2 7 1 2 6 1 2 5 1 2 4 123 122 121 120 119 118 117 116 1 1 5 1 1 4 1 1 3 1 1 2 1 1 1 1 1 0 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 3 0 3 1 3 2 3 3 3 4 3 5 3 6 1 0 9 3 7 3 8 3 9 4 0 4 1 4 2 4 3 4 4 4 5 4 6 4 7 4 8 4 9 5 0 5 1 5 2 5 3 54 55 5 6 5 7 5 8 5 9 6 0 6 1 6 2 6 3 6 4 6 5 6 6 6 7 6 8 6 9 7 0 7 1 7 2 s e g 3 5 s e g 3 6 s e g 3 7 s e g 3 9 s e g 4 0 s e g 4 1 s e g 3 8 s e g 3 4 s e g 4 2 s e g 5 0 s e g 5 1 s e g 5 2 s e g 5 4 s e g 5 3 s e g 4 4 s e g 4 5 s e g 4 6 s e g 4 7 s e g 4 8 s e g 4 3 s e g 4 9 s e g 6 / c o m 2 2 s e g 1 5 s e g 1 4 s e g 1 3 s e g 1 2 s e g 1 1 s e g 1 0 s e g 9 s e g 8 com 7 com 6 s e g 5 / c o m 2 1 s e g 4 / c o m 2 0 s e g 3 / c o m 1 9 s e g 2 / c o m 1 8 s e g 1 / c o m 1 7 seg 0 /com 16 s e g 5 5 p1 0 /a in4 p 3 0 / a i n 0 p3 1 /a in1 p3 2 /a in2 p 3 3 / a i n 3 s e g 7 / c o m 2 3 x in r e s e t p 4 7 / s r d y p 4 2 / c n t r 0 / b e e p + p 0 7 p 0 6 p 4 6 / s c l k p 4 5 / t x d p 4 4 / r x d v l 5 v s s ( n c ) c o m 1 c o m 0 c o m 3 c o m 2 s e g 5 6 c o m 5 c o m 4 s e g 2 3 s e g 2 2 s e g 2 1 s e g 2 0 s e g 1 9 s e g 1 8 s e g 1 7 s e g 1 6 s e g 3 0 s e g 2 9 s e g 2 8 s e g 2 7 s e g 2 6 s e g 2 5 s e g 2 4 s e g 3 3 s e g 3 2 s e g 3 1 s e g 5 9 s e g 6 0 / c o m 3 1 s e g 6 1 / c o m 3 0 s e g 6 3 / c o m 2 8 s e g 6 2 / c o m 2 9 s e g 5 7 s e g 5 8 s e g 6 4 / c o m 2 7 s e g 6 5 / c o m 2 6 c o m 1 5 c o m 1 4 s e g 6 6 / c o m 2 5 c o m 1 0 c o m 9 c o m 8 c o m 1 3 c o m 1 2 c o m 1 1 v ss x out oscsel x cin x c o u t nc nc p1 1 /a in5 p1 2 /a in6 p 1 3 / a i n 7 p1 4 p 1 5 p 1 6 p 1 7 p 0 0 p0 1 p 0 2 p 0 3 p0 4 p0 5 n c p 4 1 / i n t 1 / a d t p 4 0 / i n t 0 p 4 3 / c n t r 1 / b e e p - v l 4 v l 3 v l 2 v l 1 v l i n c 3 c 2 c 1 p 2 1 p 2 0 p 2 3 p 2 2 p 2 5 p 2 4 p 2 7 p 2 6 v s s n c s e g 6 7 / c o m 2 4 v c c nc m 3 8 c 8 9 m f - x x x f p 3 single-chip 8-bit cmos microcomputer mitsubishi microcomputers 38c8 group preliminar y notice: this is not a final specification. some parametric limits are subject to change. functional block diagram (package: 144p6q-a) fig. 2 functional block diagram k e y - o n w a k e - u p c n t r 0 , c n t r 1 i n t 0 , i n t 1 d a t a b u s c p u a x y s p c h p c l p s r e s e t v c c v s s r e s e t i n p u t r o m r a m l c d r a m ( 1 7 6 b y t e ) 5 15 6 1 8 v s s 5 9 i / o p o r t p 2 p 2 ( 8 ) i / o p o r t p 0 p 0 ( 8 ) i / o p o r t p 1 p 1 ( 8 ) i / o p o r t p 3 4 14 2 3 5 3 6 3 7 3 83 94 04 95 0 4 3 4 44 54 64 74 8 1 9 2 02 12 2 6 36 4 2 32 4 i / o p o r t p 4 3 23 13 0 2 9 2 8 3 4 3 3 6 5 6 6 2 7 2 52 6 p 3 ( 4 ) p 4 ( 7 ) c l o c k g e n e r a t i n g c i r c u i t c l o c k i n p u t x o u t s u b - c l o c k o u t p u t s u b - c l o c k i n p u t l c d c o n t r o l l e r t i m e r x ( 1 6 ) t i m e r y ( 1 6 ) t i m e r 1 ( 8 )t i m e r 2 ( 8 ) t i m e r 3 ( 8 ) 6 1 5 8 c o m 9 s e g 3 / c o m 1 9 s e g 4 / c o m 2 0 s e g 5 / c o m 2 1 s e g 6 / c o m 2 2 s e g 7 / c o m 2 3 s e g 8 s e g 9 s e g 1 0 s e g 1 1 s e g 1 2 c o m 1 5 c o m 1 4 c o m 1 3 c o m 1 2 c o m 1 1 c o m 1 0 s e g 0 / c o m 1 6 s e g 1 / c o m 1 7 s e g 2 / c o m 1 8 c o m 4 c o m 5 c o m 6 c o m 7 c o m 1 c o m 2 c o m 3 1 1 4 4 1 4 3 1 4 2 1 4 1 1 4 0 1 3 9 a - d c o n v e r t e r ( 1 0 ) s e r i a l i / o ( 8 ) c o m 0 c o m 8 2 5 4 3 6 x i n c l o c k o u t p u t t i m e r x c o u t 5 4 5 3 x c i n v l 5 9 8 7 v l 4 v l 3 v l 2 v l 1 1 2 1 3 1 4 1 5 c 3 c 2 c 1 v l i n 1 0 1 1 1 3 8 1 3 7 1 3 6 1 3 5 1 3 4 1 3 3 1 3 2 1 3 1 1 3 0 6 7 s e g 6 4 / c o m 2 7 s e g 6 5 / c o m 2 6 s e g 6 6 / c o m 2 5 s e g 6 7 / c o m 2 4 s e g 6 0 / c o m 3 1 s e g 6 1 / c o m 3 0 s e g 6 2 / c o m 2 9 s e g 6 3 / c o m 2 8 s e g 5 9 6 8 6 9 7 0 7 1 7 2 7 3 7 4 7 5 7 6 7 7 7 8 7 9 8 0 8 1 8 2 8 3 8 4 s e g 5 8 8 4 s e g 5 7 8 4 s e g 5 6 8 4 s e g 5 5 4 single-chip 8-bit cmos microcomputer mitsubishi microcomputers 38c8 group preliminar y notice: this is not a final specification. some parametric limits are subject to change. ? apply voltage of 4.0 C 5.5 v to v cc , and 0 v to v ss . (at high-speed mode) ? reset input pin for active l. ? input and output pins for the main clock generating circuit. ? feedback resistor is built in between x in pin and x out pin. ? connect a ceramic resonator or a quartz-crystal oscillator between the x in and x out pins to set the oscillation frequency. ? if an external clock is used, connect the clock source to the x in pin and leave the x out pin open. ? this pin determines the oscillation between x in and x out . the oscillation method can be selected from either by an oscillator or by a resistor. ? input and output pins for sub-clock generating circuit. (connect a quartz-crystal oscillator between the x cin and x cout pins to set the oscillation frequency. the clock generated the externals cannot be input directly.) ? reference voltage input pin for lcd. ? the input voltage to this pin is boosted threefold by voltage multiplier. ? lcd drive power source pins. ? lcd common output pins. ? lcd segment/common output pins. ? lcd segment output pins. ? 8-bit i/o port. ? cmos compatible input level. ? cmos 3-state output structure. ? 4-bit i/o port. ? cmos compatible input level. ? cmos 3-state output structure. ? 1-bit input port. ? cmos compatible input level. ? 7-bit i/o port. ? cmos compatible input level. ? cmos 3-state output structure. ? i/o direction register allows each pin to be individually programmed as either input or output. ? external capacitor connect pins for a voltage multiplier of lcd. ? non-function pins. ? leave the v ss (nc) pin open. ? a-d converter analog input pin ? key-on wake-up interrupt input pin ? a-d converter analog input pin ? external interrupt pin ? external interrupt pin ? a-d trigger input pin ? timer function i/o pin ? serial i/o i/o pin pin v cc , v ss reset x in x out oscsel x cin x cout v lin v l1 C v l5 com 0 C com 32 seg 0 /com 16 C seg 7 /com 23 , seg 60 com 31 C seg 67 /com 24 seg 8 C seg 59 p0 0 C p0 7 p1 4 C p1 7 p1 0 /ain 4 C p1 3 /ain 7 p2 0 C p2 7 p3 0 /ain 0 C p3 3 /ain 3 p4 0 /int 0 p4 1 /int 1 /adt p4 2 /cntr 0 / beep+, p4 3 /cntr 1 / beep- p4 4 /rxd, p4 5 /txd, p4 6 /s clk, p4 7 /s rdy c 1 , c 2 , c 3 v ss (nc), nc name power source reset input clock input clock output rc oscillation select sub-clock input sub-clock output power source input for lcd lcd power source common output segment output/ common output segment output i/o port p0 i/o port p1 i/o port p2 i/o port p3 input port p4 i/o port p4 voltage multiplier function except a port function pin description table 1 pin description function 5 single-chip 8-bit cmos microcomputer mitsubishi microcomputers 38c8 group preliminar y notice: this is not a final specification. some parametric limits are subject to change. part numbering fig. 3 part numbering m 3 8 c 89 m f C x x x f p p r o d u c t r o m / p r o m s i z e 1 : 4 0 9 6 b y t e s 2 : 8 1 9 2 b y t e s 3 : 1 2 2 8 8 b y t e s 4 : 1 6 3 8 4 b y t e s 5 : 2 0 4 8 0 b y t e s 6 : 2 4 5 7 6 b y t e s 7 : 2 8 6 7 2 b y t e s 8 : 3 2 7 6 8 b y t e s th e fi rst 128 b ytes an d t h e l ast 2 b ytes o f rom are reserved areas; they cannot be used. m e m o r y t y p e m : m a s k r o m v e r s i o n e : o n e t i m e p r o m v e r s i o n ram s i ze 0: 192 bytes 1: 256 bytes 2: 384 bytes 3: 512 bytes 4: 640 bytes 5: 768 bytes 6: 896 bytes 7: 1024 bytes 8: 1536 bytes 9: 2048 bytes p ac k age type fp: 144p6q-a package r o m n u m b e r o m i t t e d i n o n e t i m e p r o m v e r s i o n . 9 : 3 6 8 6 4 b y t e s a : 4 0 9 6 0 b y t e s b : 4 5 0 5 6 b y t e s c : 4 9 1 5 2 b y t e s d : 5 3 2 4 8 b y t e s e : 5 7 3 4 4 b y t e s f : 6 1 4 4 0 b y t e s 6 single-chip 8-bit cmos microcomputer mitsubishi microcomputers 38c8 group preliminar y notice: this is not a final specification. some parametric limits are subject to change. group expansion mitsubishi plans to expand the 38c8 group as follows. memory type support for mask rom and one time prom versions memory size rom/prom size ............................................................ 60 k bytes ram size ........................................................................ 2048 bytes memory expansion plan fig. 4 memory expansion plan currently planning products are listed below. as of dec. 2000 package 144p6q-a 144p6q-a product name m38c89mf-xxxfp m38c89effp (p) rom size (bytes) rom size for user in ( ) 61440 (61310) 61440 (61310) ram size (bytes) 2048 2048 table 2 support products mask rom version one time prom version remarks packages 144p6q-a ................................... 0.5 mm-pitch plastic molded qfp 3 2 k 28k 24k 20k 16k 1 2 k 8k 4k 2 5 63 8 45 1 2 640 7 6 88 9 6 1,024 192 4 0 k 4 8 k 1 , 5 3 62 , 0 4 8 56k 6 0 k r o m s i z e ( b y t e s ) r a m s i z e ( b y t e s ) m38c89mf/ef u n d e r d e v e l o p m e n t p r o d u c t s u n d e r d e v e l o p m e n t o r p l a n n i n g : t h e d e v e l o p m e n t s c h e d u l e a n d s p e c i f i c a t i o n m a y b e r e v i s e d w i t h o u t n o t i c e . t h e d e v e l o p m e n t o f p l a n n i n g p r o d u c t s m a y b e s t o p p e d . 7 single-chip 8-bit cmos microcomputer mitsubishi microcomputers 38c8 group preliminar y notice: this is not a final specification. some parametric limits are subject to change. functional description central processing unit (cpu) the 38c8 group uses the standard 740 family instruction set. refer to the table of 740 family addressing modes and machine instruc- tions or the 740 family software manual for details on the instruction set. machine-resident 740 family instructions are as follows: the fst and slw instruction cannot be used. the stp, wit, mul, and div instruction can be used. [accumulator (a)] the accumulator is an 8-bit register. data operations such as data transfer, etc., are executed mainly through the accumulator. [index register x (x)] the index register x is an 8-bit register. in the index addressing modes, the value of the operand is added to the contents of register x and specifies the real address. [index register y (y)] the index register y is an 8-bit register. in partial instruction, the value of the operand is added to the contents of register y and specifies the real address. [stack pointer (s)] the stack pointer is an 8-bit register used during subroutine calls and interrupts. this register indicates start address of stored area (stack) for storing registers during subroutine calls and interrupts. the low-order 8 bits of the stack address are determined by the con- tents of the stack pointer. the high-order 8 bits of the stack address are determined by the stack page selection bit. if the stack page selection bit is 0 , the high-order 8 bits becomes 00 16 . if the stack page selection bit is 1 , the high-order 8 bits becomes 01 16 . the operations of pushing register contents onto the stack and pop- ping them from the stack are shown in figure 6. store registers other than those described in figure 6 with program when the user needs them during interrupts or subroutine calls. [program counter (pc)] the program counter is a 16-bit counter consisting of two 8-bit regis- ters pc h and pc l . it is used to indicate the address of the next in- struction to be executed. fig. 5 740 family cpu register structure a accumulator b7 b7 b7 b7 b0 b7 b15 b0 b7 b0 b0 b0 b0 x index register x y index register y s stack pointer pc l program counter pc h n v t b d i z c processor status register (ps) carry flag zero flag interrupt disable flag decimal mode flag break flag index x mode flag overflow flag negative flag 8 single-chip 8-bit cmos microcomputer mitsubishi microcomputers 38c8 group preliminar y notice: this is not a final specification. some parametric limits are subject to change. table 3 push and pop instructions of accumulator or processor status register accumulator processor status register push instruction to stack pha php pop instruction from stack pla plp fig. 6 register push and pop at interrupt generation and subroutine call note : condition for acceptance of an interrupt interrupt enable flag is 1 e x e c u t e j s r o n - g o i n g r o u t i n e m ( s )( p c h ) ( s ) ( s ) C 1 m ( s )( p c l ) e x e c u t e r t s ( p c l )m ( s ) (s) (s) C 1 ( s ) ( s ) + 1 (s) (s) + 1 ( p c h )m ( s ) subroutine pop return address from stack p u s h r e t u r n a d d r e s s o n s t a c k m ( s )( p s ) execute rti (ps) m (s) ( s ) ( s ) C 1 ( s ) ( s ) + 1 interrupt service routine pop contents of processor status register from stack m (s) (pc h ) ( s ) ( s ) C 1 m ( s )( p c l ) ( s ) ( s ) C 1 (pc l )m (s) ( s ) ( s ) + 1 ( s ) ( s ) + 1 (pc h )m (s) pop return address from stack i flag is set from 0 to 1 fetch the jump vector push return address on stack push contents of processor status register on stack interrupt request (note) i n t e r r u p t d i s a b l e f l a g i s 0 9 single-chip 8-bit cmos microcomputer mitsubishi microcomputers 38c8 group preliminar y notice: this is not a final specification. some parametric limits are subject to change. [processor status register (ps)] the processor status register is an 8-bit register consisting of 5 flags which indicate the status of the processor after an arithmetic opera- tion and 3 flags which decide mcu operation. branch operations can be performed by testing the carry (c) flag , zero (z) flag, overflow (v) flag, or the negative (n) flag. in decimal mode, the z, v, n flags are not valid. ? bit 0: carry flag (c) the c flag contains a carry or borrow generated by the arithmetic logic unit (alu) immediately after an arithmetic operation. it can also be changed by a shift or rotate instruction. ? bit 1: zero flag (z) the z flag is set if the result of an immediate arithmetic operation or a data transfer is 0 , and cleared if the result is anything other than 0 . ? bit 2: interrupt disable flag (i) the i flag disables all interrupts except for the interrupt generated by the brk instruction. interrupts are disabled when the i flag is 1 . ? bit 3: decimal mode flag (d) the d flag determines whether additions and subtractions are executed in binary or decimal. binary arithmetic is executed when this flag is 0 ; decimal arithmetic is executed when it is 1 . decimal correction is automatic in decimal mode. only the adc ? bit 4: break flag (b) the b flag is used to indicate that the current interrupt was generated by the brk instruction. the brk flag in the processor status register is always 0 . when the brk instruction is used to generate an interrupt, the processor status register is pushed onto the stack with the break flag set to 1 . ? bit 5: index x mode flag (t) when the t flag is 0 , arithmetic operations are performed between accumulator and memory. when the t flag is 1 , direct arithmetic operations and direct data transfers are enabled between memory locations. ? bit 6: overflow flag (v) the v flag is used during the addition or subtraction of one byte of signed data. it is set if the result exceeds +127 to -128. when the bit instruction is executed, bit 6 of the memory location operated on by the bit instruction is stored in the overflow flag. ? bit 7: negative flag (n) the n flag is set if the result of an arithmetic operation or data transfer is negative. when the bit instruction is executed, bit 7 of the memory location operated on by the bit instruction is stored in the negative flag. table 4 set and clear instructions of each bit of processor status register set instruction clear instruction c flag sec clc z flag C C i flag sei cli d flag sed cld b flag C C t flag set clt v flag C clv n flag C C 10 single-chip 8-bit cmos microcomputer mitsubishi microcomputers 38c8 group preliminar y notice: this is not a final specification. some parametric limits are subject to change. [cpu mode register (cpum)] 003b 16 the cpu mode register contains the stack page selection bit and the internal system clock selection bit. the cpu mode register is allocated at address 003b 16 . fig. 7 structure of cpu mode register n o t a v a i l a b l e p rocessor mo d e bi ts b1 b0 0 0 : single-chip mode 0 1 : 1 0 : 1 1 : stack page selection bit 0 : 0 page 1 : 1 page not used (returns 1 when read) (do not write 0 to this bit) sub-clock (x cin C x cout ) stop bit 0 : stopped 1 : oscillating main clock (x in C x out ) stop bit 0 : oscillating 1 : stopped main clock division ratio selection bit 0 : f(x in )/2 (high-speed mode) 1 : f(x in )/8 (middle-speed mode) internal system clock selection bit 0 : x in C x out selected (middle-/high-speed mode) 1 : x cin C x cout selected (low-speed mode) cpu mo d e reg i ster ( c p u m ( c m ) : a d d r e s s 0 0 3 b 1 6 ) b 7 b 0 11 single-chip 8-bit cmos microcomputer mitsubishi microcomputers 38c8 group preliminar y notice: this is not a final specification. some parametric limits are subject to change. memory special function register (sfr) area the special function register area in the zero page contains control registers such as i/o ports and timers. ram ram is used for data storage and for stack area of subroutine calls and interrupts. rom the first 128 bytes and the last 2 bytes of rom are reserved for device testing and the rest is user area for storing programs. interrupt vector area the interrupt vector area contains reset and interrupt vectors. zero page access to this area with only 2 bytes is possible in the zero page addressing mode. special page access to this area with only 2 bytes is possible in the special page addressing mode. fig. 8 memory map diagram 192 256 384 512 640 768 896 1024 1536 2048 0 0 f f 1 6 0 1 3 f 1 6 0 1 b f 1 6 0 2 3 f 1 6 0 2 b f 1 6 0 3 3 f 1 6 0 3 b f 1 6 0 4 3 f 1 6 0 6 3 f 1 6 0 8 3 f 1 6 r a m a r e a r a m s i z e ( b y t e s ) a d d r e s s x x x x 1 6 4 0 9 6 8 1 9 2 1 2 2 8 8 1 6 3 8 4 2 0 4 8 0 2 4 5 7 6 2 8 6 7 2 3 2 7 6 8 3 6 8 6 4 4 0 9 6 0 4 5 0 5 6 4 9 1 5 2 5 3 2 4 8 5 7 3 4 4 6 1 4 4 0 f 0 0 0 1 6 e 0 0 0 1 6 d 0 0 0 1 6 c 0 0 0 1 6 b 0 0 0 1 6 a 0 0 0 1 6 9 0 0 0 1 6 8 0 0 0 1 6 7 0 0 0 1 6 6 0 0 0 1 6 5 0 0 0 1 6 4 0 0 0 1 6 3 0 0 0 1 6 20 0 0 1 6 10 0 0 1 6 f 080 16 e080 16 d080 16 c080 16 b080 16 a080 16 9080 16 8080 16 7080 16 6080 16 5080 16 4080 16 3080 16 2080 16 1080 16 r o m a r e a r o m s i z e ( b y t e s ) add ress yyyy 16 add ress zzzz 16 0000 16 0040 16 0 4 3 0 1 6 f f 0 0 1 6 f f d c 1 6 f f f e 1 6 ffff 16 x x x x 1 6 yyyy 16 zzzz 16 ram rom s f r a r e a n ot use d i nterrupt vector are a r e s e r v e d r o m a r e a ( 1 2 8 b y t e s ) z e r o p a g e s p e c i a l p a g e lcd display ram area ? r eserve d rom area 0130 16 0840 16 ? the stard address of the lcd display area can be switched either zero page (addresses 0040 16 C 00ef 16 ) or 3 page (addresses 0340 16 C 03ef 16 ) by software. immediately after reset released, 3 page is selected. 0 3 4 0 1 6 l c d d i s p l a y r a m a r e a ? 12 single-chip 8-bit cmos microcomputer mitsubishi microcomputers 38c8 group preliminar y notice: this is not a final specification. some parametric limits are subject to change. fig. 9 memory map of special function register (sfr) t ransm i t/ r ece i ve b u ff er reg i ster (tb / rb) 0020 16 0021 16 0022 16 0023 16 0024 16 0025 16 0026 16 0027 16 0028 16 0029 16 0 0 2 a 1 6 0 0 2 b 1 6 002 c 16 002 d 16 002 e 16 002 f 16 0030 16 0031 16 0032 16 0033 16 0034 16 0035 16 0036 16 0037 16 0038 16 0039 16 0 0 3 a 1 6 0 0 3 b 1 6 0 0 3 c 1 6 0 0 3 d 1 6 0 0 3 e 1 6 003 f 16 0 0 0 0 1 6 0 0 0 1 1 6 0 0 0 2 1 6 0 0 0 3 1 6 0 0 0 4 1 6 0 0 0 5 1 6 0 0 0 6 1 6 0 0 0 7 1 6 0 0 0 8 1 6 0009 16 000 a 16 0 0 0 b 1 6 0 0 0 c 1 6 0 0 0 d 1 6 0 0 0 e 1 6 0 0 0 f 1 6 0010 16 0 0 1 1 1 6 0012 16 0013 16 0 0 1 4 1 6 0 0 1 5 1 6 0 0 1 6 1 6 0 0 1 7 1 6 0 0 1 8 1 6 0019 16 001 a 16 001 b 16 001 c 16 001 d 16 001 e 16 001 f 16 p ort p 0 (p 0 ) p o r t p 0 d i r e c t i o n r e g i s t e r ( p 0 d ) p o r t p 1 ( p 1 ) p o r t p 1 d i r e c t i o n r e g i s t e r ( p 1 d ) p ort p 2 (p 2 ) p o r t p 2 d i r e c t i o n r e g i s t e r ( p 2 d ) p o r t p 3 ( p 3 ) p o r t p 4 ( p 4 ) p ort p 4 di rect i on reg i ster (p 4 d) s e r i a l i / o s t a t u s r e g i s t e r ( s i o s t s ) s er i a l i / o contro l reg i ster (siocon) uart contro l reg i ster (uartcon) i n t e r r u p t c o n t r o l r e g i s t e r 2 ( i c o n 2 ) ti mer x mo d e reg i ster (txm) i nterrupt e d ge se l ect i on reg i ster (intedge) cpu mo d e reg i ster (cpum) i nterrupt request reg i ster 1 (ireq 1 ) i nterrupt request reg i ster 2 (ireq 2 ) i nterrupt contro l reg i ster 1 (icon 1 ) ti mer x (l ow-or d er ) (txl) p u l l r e g i s t e r a ( p u l l a ) p u l l r e g i s t e r b ( p u l l b ) l c d c o n t r o l r e g i s t e r 1 ( l c 1 ) a - d c o n t r o l r e g i s t e r ( a d c o n ) a - d convers i on reg i ster (l ow-or d er ) (adl) a - d convers i on reg i ster (hi g h -or d er ) (adh) p o r t p 3 d i r e c t i o n r e g i s t e r ( p 3 d ) b a u d r a t e g e n e r a t o r ( b r g ) t i m e r x ( h i g h - o r d e r ) ( t x h ) t i m e r y ( l o w - o r d e r ) ( t y l ) t i m e r y ( h i g h - o r d e r ) ( t y h ) t i m e r 1 ( t 1 ) t i m e r 2 ( t 2 ) t i m e r 3 ( t 3 ) t i m e r y m o d e r e g i s t e r ( t y m ) t i m e r 1 2 3 m o d e r e g i s t e r ( t 1 2 3 m ) l c d c o n t r o l r e g i s t e r 2 ( l c 2 ) l c d m o d e r e g i s t e r ( l m ) 13 single-chip 8-bit cmos microcomputer mitsubishi microcomputers 38c8 group preliminar y notice: this is not a final specification. some parametric limits are subject to change. i/o ports [direction registers] the i/o ports p0 C p3 and p4 1 C p4 7 have direction registers which determine the input/output direction of each individual pin. each bit in a direction register corresponds to one pin, each pin can be set to be input port or output port. when 0 is written to the bit corresponding to a pin, that pin be- comes an input pin. when 1 is written to that bit, that pin becomes an output pin. if data is read from a pin set to output, the value of the port output latch is read, not the value of the pin itself. pins set to input are float- ing. if a pin set to input is written to, only the port output latch is written to and the pin remains floating. pull-up control by setting the pull register a (address 0016 16 ) or the pull register b (address 0017 16 ), ports p0 to p4 except for port p4 0 can control pull-up with a program. however, the contents of pull register a and pull register b do not affect ports programmed as the output ports. fig. 10 structure of pull register a and pull register b p 0 0 C p 0 3 p u l l - u p p 0 4 C p 0 7 p u l l - u p p 1 0 C p 1 3 p u l l - u p p 1 4 C p 1 7 p u l l - u p p 2 0 C p 2 3 p u l l - u p p 2 4 C p 2 7 p u l l - u p p 3 0 C p 3 3 p u l l - u p n o t u s e d ( r e t u r n 0 w h e n r e a d ) pull register a (pulla: address 0016 16 ) 0: no pull-up 1: pull-up b7 b0 n o t e : t h e c o n t e n t s o f p u l l r e g i s t e r a a n d p u l l r e g i s t e r b d o n o t a f f e c t p o r t s p r o g r a m m e d a s t h e o u t p u t p o r t . n o t u s e d ( r e t u r n 0 w h e n r e a d ) p 4 1 p u l l - u p p 4 2 p u l l - u p p 4 3 p u l l - u p p 4 4 p u l l - u p p 4 5 p u l l - u p p 4 6 p u l l - u p p 4 7 p u l l - u p b 7b0 pull register b (pullb: address 0017 16 ) 14 single-chip 8-bit cmos microcomputer mitsubishi microcomputers 38c8 group preliminar y notice: this is not a final specification. some parametric limits are subject to change. table 5 list of i/o port function pin p0 0 C p0 7 p1 0 /an 4 C p1 3 /an 7 p1 4 C p1 7 p2 0 C p2 7 p3 0 /an 0 C p3 3 /an 3 p4 0 /int 0 p4 1 /int 1 p4 2 /cntr 0 / beep+ p4 3 /cntr 1 / beep- p4 4 /rxd p4 5 /txd p4 6 /s clk p4 7 /s rdy com 0 C com 7 , com 8 C com 15 seg 0 /com 16 C seg 7 /com 23 , seg 60 /com 31 C seg 67 /com 24 seg 8 C seg 59 name port p0 port p1 port p2 port p3 port p4 common segment/ common segment input/output input/output, individual bits input/output, individual bits input/output, individual bits input input/output, individual bits output i/o format cmos 3-state output cmos compatible input level cmos 3-state output cmos 3-state output cmos compatible input level cmos compatible input level cmos 3-state output lcd common output lcd segment output lcd common ouput lcd segment output non-port function key input (key-on wake-up) interrupt in- put a-d converter input external interrupt in- put timer x function i/o timer y function input serial i/o funtion i/o related sfrs pull register a pull register a a-d control register pull register a pull register a interrupt control register 2 pull register a a-d control register pull register b interrupt edge select register pull register b timer x mode register pull register b timer y mode register pull register b serial i/o control register serial i/o status register uart control register lcd mode register ref. no. (1) (2) (1) (1) (2) (3) (1) (4) (5) (6) (7) (8) (9) 15 single-chip 8-bit cmos microcomputer mitsubishi microcomputers 38c8 group preliminar y notice: this is not a final specification. some parametric limits are subject to change. fig. 11 port block diagram (1) ( 1 ) p o r t s p 0 , p 1 4 C p 1 7 , p 2 , p 4 1 e x c e p t p 0 , p 1 d a t a b u s d i r e c t i o n r e g i s t e r p o r t l a t c h p u l l - u p c o n t r o l k e y - o n w a k e - u p i n t e r r u p t i n p u t i n t 1 i n t e r r u p t i n p u t , a d t ( 2 ) p o r ts p 1 0 C p 1 3 , p 3 a n a l o g i n p u t p i n s e l e c t i o n b i t a-d converter input ( 4 ) p o r t p 4 2 b u z z e r o u t p u t m o d e t i m e r o u t p u t c n t r 0 i n t e r r u p t i n p u t ( 5 ) p o r t p 4 3 p o r t l a t c h data bus int 0 interrupt input d a t a b u s (3) port p 4 0 p u l l - u p c o n t r o l d i r e c t i o n r e g i s t e r port latch data bus p u l l - u p c o n t r o l d i r e c t i o n r e g i s t e r p o r t l a t c h d a t a b u s buzzer output mode timer output cntr 1 interrupt input pull-up control direction register 16 single-chip 8-bit cmos microcomputer mitsubishi microcomputers 38c8 group preliminar y notice: this is not a final specification. some parametric limits are subject to change. fig. 12 port block diagram (2) (9) port p4 7 serial i/o ready output s e r i a l i / o m o d e s e l e c t i o n b i t s e r i a l i / o e n a b l e b i t s r d y o u t p u t e n a b l e b i t (8) port p4 6 s e r i a l i / o s y n c h r o n o u s c l o c k s e l e c t i o n b i t serial i/o clock output serial i/o mode selection bi t serial i/o enable bi t ( 6 ) p o r t p 4 4 ( 7 ) p o r t p 4 5 d a t a b u s s e r i a l i / o e n a b l e b i t t r a n s m i t e n a b l e b i t serial i/o output p4 5 /txd p-channel output disable bit pull-up control d a t a b u s s e r i a l i / o e n a b l e b i t r e c e i v e e n a l b l e b i t s e r i a l i / o i n p u t p o r t l a t c h pull-up control d i r e c t i o n r e g i s t e r p o r t l a t c h direction register s e r i a l i / o e n a b l e b i t pull-up control direction register port latch data bus serial i/o clock input p u l l - u p c o n t r o l direction register p o r t l a t c h data bus 17 single-chip 8-bit cmos microcomputer mitsubishi microcomputers 38c8 group preliminar y notice: this is not a final specification. some parametric limits are subject to change. interrupts interrupts occur by fifteen sources: six external, eight internal, and one software. interrupt control each interrupt except the brk instruction interrupt have both an in- terrupt request bit and an interrupt enable bit, and is controlled by the interrupt disable flag. an interrupt occurs if the corresponding inter- rupt request and enable bits are 1 and the interrupt disable flag is 0 . interrupt enable bits can be set or cleared by software. interrupt re- quest bits can be cleared by software, but cannot be set by software. the brk instruction interrupt and reset cannot be disabled with any flag or bit. the i flag disables all interrupts except the brk instruction interrupt and reset. if several interrupts requests occurs at the same time the interrupt with highest priority is accepted first. interrupt operation by acceptance of an interrupt, the following operations are automati- cally performed: 1. the processing being executed is stopped. 2. the contents of the program counter and processor status reg- ister are automatically pushed onto the stack. 3. the interrupt disable flag is set and the corresponding interrupt request bit is cleared. 4. the interrupt jump destination address is read from the vector table into the program counter. notes on interrupts when setting the followings, the interrupt request bit may be set to 1 . ? when setting external interrupt active edge related register: interrupt edge selection register (address 3a 16 ) timer x mode register (address 27 16 ) timer y mode register (address 28 16 ) ? when switching interrupt sources of an interrupt vector address where two or more interrupt sources are allocated related register: ad control regsiter (address 31 16 ) when not requiring for the interrupt occurrence synchronized with these setting, take the following sequence. ? set the corresponding interrupt enable bit to 0 (disabled). ? set the interrupt edge select bit (active edge switch bit) or the inter- rupt source select bit to 1 . ? set the corresponding interrupt request bit to 0 after 1 or more instructions have been executed. ? set the corresponding interrupt enable bit to 1 (enabled). interrupt source reset (note 2) int 0 int 1 serial i/o reception serial i/o transmission timer x timer y timer 2 timer 3 cntr 0 cntr 1 timer 1 key input (key- on wake-up) a-d conversion brk instruction priority 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 vector addresses (note 1) high fffd 16 fffb 16 fff9 16 fff7 16 fff5 16 fff3 16 fff1 16 ffef 16 ffed 16 ffeb 16 ffe9 16 ffe7 16 ffe1 16 ffdf 16 ffdd 16 interrupt request generating conditions at reset at detection of either rising or falling edge of int 0 intput at detection of either rising or falling edge of int 1 input at completion of serial i/o data reception at completion of serial i/o transmission shift or when transmission buffer is empty at timer x underflow at timer y underflow at timer 2 underflow at timer 3 underflow at detection of either rising or falling edge of cntr 0 input at detection of either rising or falling edge of cntr 1 input at timer 1 underflow at falling of port p2 (at input) input logical level and at completion of a-d conversion at brk instruction execution remarks non-maskable external interrupt (active edge selectable) external interrupt (active edge selectable) valid when serial i/o is selected valid when serial i/o is selected external interrupt (active edge selectable) external interrupt (active edge selectable) external interrupt (falling valid) valid when a-d conversion interrupt is selected non-maskable software interrupt low fffc 16 fffa 16 fff8 16 fff6 16 fff4 16 fff2 16 fff0 16 ffee 16 ffec 16 ffea 16 ffe8 16 ffe6 16 ffe0 16 ffde 16 ffdc 16 notes 1: vector addresses contain interrupt jump destination addresses. 2: reset function in the same way as an interrupt with the highest priority. table 6 interrupt vector addresses and priority 18 single-chip 8-bit cmos microcomputer mitsubishi microcomputers 38c8 group preliminar y notice: this is not a final specification. some parametric limits are subject to change. fig. 13 interrupt control fig. 14 structure of interrupt-related registers i n t e r r u p t r e q u e s t b i t i n t e r r u p t e n a b l e b i t i n t e r r u p t d i s a b l e f l a g ( i ) b r k i n s t r u c t i o n r e s e t i n t e r r u p t r e q u e s t i n t e r r u p t r e q u e s t r e g i s t e r 1 i n t 0 i n t e r r u p t r e q u e s t b i t i n t 1 i n t e r r u p t r e q u e s t b i t s e r i a l i / o r e c e i v e i n t e r r u p t r e q u e s t b i t s e r i a l i / o t r a n s m i t i n t e r r u p t r e q u e s t b i t t i m e r x i n t e r r u p t r e q u e s t b i t t i m e r y i n t e r r u p t r e q u e s t b i t t i m e r 2 i n t e r r u p t r e q u e s t b i t t i m e r 3 i n t e r r u p t r e q u e s t b i t 0 : n o i nterrupt request i ssue d 1 : interrupt request issued ( i r e q 1 : a d d r e s s 0 0 3 c 1 6 ) i n t e r r u p t r e q u e s t r e g i s t e r 2 cntr 0 i nterrupt request bi t cntr 1 interrupt request bit timer 1 interrupt request bit not used (returns 0 when read) key input interrupt request bit ad conversion interrupt request bit not used (returns 0 when read) (ireq 2 : a dd ress 003 d 16 ) b 7 b 0 i n t e r r u p t e d g e s e l e c t i o n r e g i s t e r i n t 0 i n t e r r u p t e d g e s e l e c t i o n b i t i n t 1 i n t e r r u p t e d g e s e l e c t i o n b i t n o t u s e d ( r e t u r n 0 w h e n r e a d ) (intedge : a dd ress 003 a 16 ) 0 : f a l l i n g e d g e a c t i v e 1 : r i s i n g e d g e a c t i v e b 7 b 0 b 7 b 0 i nterrupt contro l reg i ster 1 i n t 0 i n t e r r u p t e n a b l e b i t i n t 1 i n t e r r u p t e n a b l e b i t s e r i a l i / o r e c e i v e i n t e r r u p t e n a b l e b i t s e r i a l i / o t r a n s m i t i n t e r r u p t e n a b l e b i t t i m e r x i n t e r r u p t e n a b l e b i t t i m e r y i n t e r r u p t e n a b l e b i t t i m e r 2 i n t e r r u p t e n a b l e b i t t i m e r 3 i n t e r r u p t e n a b l e b i t ( i c o n 1 : a d d r e s s 0 0 3 e 1 6 ) i nterrupt contro l reg i ster 2 c n t r 0 i n t e r r u p t e n a b l e b i t c n t r 1 i n t e r r u p t e n a b l e b i t t i m e r 1 i n t e r r u p t e n a b l e b i t n o t u s e d ( r e t u r n s 0 w h e n r e a d ) ( d o n o t w r i t e 1 t o t h i s b i t ) k e y i n p u t i n t e r r u p t e n a b l e b i t a d c o n v e r s i o n i n t e r r u p t e n a b l e b i t n o t u s e d ( r e t u r n s 0 w h e n r e a d ) ( d o n o t w r i t e 1 t o t h i s b i t ) 0 : i nterrupts di sa bl e d 1 : interrupts enabled ( i c o n 2 : a d d r e s s 0 0 3 f 1 6 ) b 7 b 0 b 7 b 0 19 single-chip 8-bit cmos microcomputer mitsubishi microcomputers 38c8 group preliminar y notice: this is not a final specification. some parametric limits are subject to change. key input interrupt (key-on wake-up) a key input interrupt request is generated by applying l level to any pin of port p2 that have been set to input mode. in other words, it is generated when and of input level goes from 1 to 0 . an example of using a key input interrupt is shown in figure 15, where an inter- rupt request is generated by pressing one of the keys consisted as an active-low key matrix which inputs to ports p2 0 C p2 3 . fig. 15 connection example when using key input interrupt and port p2 block diagram ? ?? ? ?? ? ?? ? ?? ? ?? ? ?? ? ?? ? ?? port p2 0 latch port p2 1 latch port p2 2 latch port p2 3 latch port p2 4 latch port p2 5 latch port p2 6 latch key input control register = 1 port p2 7 latch key input control register = 1 p 2 0 i n p u t p2 1 input p 2 2 i n p u t p 2 3 i n p u t p2 4 output p2 5 output p2 6 output p 2 7 o u t p u t p u l l r e g i s t e r a b i t 2 = 1 port p2 input reading circuit p o r t p x x l l e v e l o u t p u t ? p-channel transistor for pull-up ?? cmos output buffer key input interrupt request k e y i n p u t c o n t r o l r e g i s t e r = 1 key input control register = 1 key input control register = 1 k e y i n p u t c o n t r o l r e g i s t e r = 1 key input control register = 1 k e y i n p u t c o n t r o l r e g i s t e r = 1 p o r t p 2 7 d i r e c t i o n r e g i s t e r = 1 p o r t p 2 6 d i r e c t i o n r e g i s t e r = 1 p o r t p 2 5 d i r e c t i o n r e g i s t e r = 1 port p2 4 direction register = 1 port p2 3 direction register = 0 port p2 2 direction register = 0 port p2 1 direction register = 0 p o r t p 2 0 d i r e c t i o n r e g i s t e r = 0 20 single-chip 8-bit cmos microcomputer mitsubishi microcomputers 38c8 group preliminar y notice: this is not a final specification. some parametric limits are subject to change. timers the 38c8 group has five timers: timer x, timer y, timer 1, timer 2, and timer 3. timer x and timer y are 16-bit timers, and timer 1, timer 2, and timer 3 are 8-bit timers. all timers are down count timers. when the timer reaches 00 16 , an underflow occurs at the next count pulse and the corresponding timer latch is reloaded into the timer and the count is continued. when a timer underflows, the interrupt request bit corresponding to that timer is set to 1. read and write operation on 16-bit timer must be performed for both high and low-order bytes. when reading a 16-bit timer, read the high- order byte first. when writing to a 16-bit timer, write the low-order byte first. the 16-bit timer cannot perform the correct operation when reading during the write operation, or when writing during the read operation. fig. 16 timer block diagram 10 timer y stop control bit falling edge detection period measure- ment mode t i m e r y i n t e r r u p t r e q u e s t pulse width hl continuously measurement mode rising edge detection 00 , 01 , 11 timer y operating mode bits t i m e r x i n t e r r u p t r e q u e s t timer x (low) (8) t i m e r x ( h i g h ) ( 8 ) t i m e r x ( l o w ) l a t c h ( 8 ) q q t s 0 1 1 0 f ( x i n ) / 1 6 ( f ( x c i n ) / 1 6 i n l o w - s p e e d m o d e ? 00 , 01 , 11 c n t r 0 a c t i v e e d g e s w i t c h b i t c n t r 0 a c t i v e e d g e s w i t c h b i t p u l s e o u t p u t m o d e t i m e r 2 l a t c h ( 8 ) timer 2 (8) 1 1 f ( x c i n ) / 3 2 t i m e r 1 i n t e r r u p t r e q u e s t data bus ? 0 0 , 0 1 , 1 0 11 0 0 , 1 1 01 timer x operating mode bits p 4 3 / c n t r 1 / b e e p - p 4 2 / c n t r 0 / b e e p + 0 1 pulse width measurement mode b u z z e r o u t p u t m o d e p4 2 latch p 4 2 d i r e c t i o n r e g i s t e r beep- valid bit f(x cin ) 0 1 f ( x i n ) t i m e r x c o u n t s o u r c e s e l e c t i o n b i t f ( x c i n ) / 3 2 timer x operating mode bits timer x stop control bit timer x write control bit t i m e r x ( h i g h ) l a t c h ( 8 ) cntr 1 active edge switch bit p 4 3 d i r e c t i o n r e g i s t e r p4 3 latch f(x in )/16 (f(x cin )/16 in low-speed mode ? 1 0 t i m e r y ( l o w ) ( 8 ) timer y (high) (8) t i m e r y ( l o w ) l a t c h ( 8 ) timer y (low) high (8) f(x in )/16 (f(x cin )/16 in low-speed mode ? ? 0 0 t i m e r 1 l a t c h ( 8 ) timer 1 (8) 1 0 timer 3 count source selection bit 21 single-chip 8-bit cmos microcomputer mitsubishi microcomputers 38c8 group preliminar y notice: this is not a final specification. some parametric limits are subject to change. timer x timer x is a 16-bit timer that can be selected in one of four modes and can be controlled the timer x write by setting the timer x mode register. (1) timer mode when the timer x count source selection bit is 0 , the timer counts f(x in )/16 (or f(x cin )/16 in low-speed mode). when it is 1 , the timer counts f(x in ). (2) buzzer output mode each time the timer underflows, a signal output from the beep + pin is inverted. when the beep- valid bit is 1 , the opposite phase of beep+ signal is output from the beep- pin. when using the beep+ pin and the beep- pin, set ports shared with these pins to output. (3) event counter mode the timer counts signals input through the cntr 0 pin. except for this, the operation in event counter mode is the same as in timer mode. when using a timer in this mode, set the port shared with the cntr 0 pin to input. (4) pulse width measurement mode when the timer x count source selection bit is 0 , the count source is f(x in )/16 (or f(x cin )/16 in low-speed mode). when it is 1 , the count source is f(x in ). if cntr 0 active edge switch bit is 0 , the timer counts while the input signal of cntr 0 pin is at h . if it is 1 , the timer counts while the input signal of cntr 0 pin is at l . when using a timer in this mode, set the port shared with the cntr 0 pin to input. timer x write control if the timer x write control bit is 0 , when the value is written in the address of timer x, the value is loaded in the timer x and the latch at the same time. if the timer x write control bit is 1 , when the value is written in the address of timer x, the value is loaded only in the latch. the value in the latch is loaded in timer x after timer x underflows. if the value is written in latch only, unexpected value may be set in the high-order counter when the writing in high-order latch and the underflow of timer x are performed at the same timing. notes on cntr 0 interrupt active edge selection cntr 0 interrupt active edge depends on the cntr 0 active edge switch bit. fig. 17 structure of timer x mode register t i m e r x m o d e r e g i s t e r ( t x m : a d d r e s s 0 0 2 7 1 6 ) t i m e r x w r i t e c o n t r o l b i t 0 : w r i t e v a l u e i n l a t c h a n d c o u n t e r 1 : w r i t e v a l u e i n l a t c h o n l y b e e p - v a l i d b i t 0 : i n v a l i d 1 : v a l i d n o t u s e d t i m e r x o p e r a t i n g m o d e b i t s b 5 b 4 0 0 : t i m e r m o d e 0 1 : b u z z e r o u t p u t m o d e 1 0 : e v e n t c o u n t e r m o d e 1 1 : p u l s e w i d t h m e a s u r e m e n t m o d e c n t r 0 a c t i v e e d g e s w i t c h b i t 0 : c o u n t a t r i s i n g e d g e i n e v e n t c o u n t e r m o d e s t a r t f r o m h o u t p u t i n p u l s e o u t p u t m o d e m e a s u r e h p u l s e w i d t h i n p u l s e w i d t h m e a s u r e m e n t m o d e f a l l i n g e d g e a c t i v e f o r i n t e r r u p t 1 : c o u n t a t f a l l i n g e d g e i n e v e n t c o u n t e r m o d e s t a r t f r o m l o u t p u t i n p u l s e o u t p u t m o d e m e a s u r e l p u l s e w i d t h i n p u l s e w i d t h m e a s u r e m e n t m o d e r i s i n g e d g e a c t i v e f o r i n t e r r u p t t i m e r x s t o p c o n t r o l b i t 0 : c o u n t s t a r t 1 : c o u n t s t o p b 7 b 0 22 single-chip 8-bit cmos microcomputer mitsubishi microcomputers 38c8 group preliminar y notice: this is not a final specification. some parametric limits are subject to change. timer y timer y is a 16-bit timer that can be selected in one of four modes. (1) timer mode the timer counts f(x in )/16 (or f(x cin )/16 in low-speed mode). (2) period measurement mode cntr 1 interrupt request is generated at rising/falling edge of cntr 1 pin input signal. simultaneously, the value in timer y latch is reloaded in timer y and timer y continues counting down. except for the above- mentioned, the operation in period measurement mode is the same as in timer mode. the timer value just before the reloading at rising/falling of cntr 1 pin input signal is retained until the timer y is read once after the reload. the rising/falling timing of cntr 1 pin input signal is found by cntr 1 interrupt. when using a timer in this mode, set the port shared with the cntr 1 pin to input. (3) event counter mode the timer counts signals input through the cntr 1 pin. except for this, the operation in event counter mode is the same as in timer mode. when using a timer in this mode, set the port shared with the cntr 1 pin to input. (4) pulse width hl continuously measurement mode cntr 1 interrupt request is generated at both rising and falling edges of cntr 1 pin input signal. except for this, the operation in pulse width hl continuously measurement mode is the same as in period measurement mode. when using a timer in this mode, set the port shared with the cntr 1 pin to input. notes on cntr 1 interrupt active edge selection cntr 1 interrupt active edge depends on the cntr 1 active edge switch bit. however, in the pulse width hl continuously measure- ment mode, cntr 1 interrupt request is generated at both rising and falling edges of cntr 1 pin input signal regardless of the setting of cntr 1 active edge switch bit. fig. 18 structure of timer y mode register t i m e r y m o d e r e g i s t e r ( t y m : a d d r e s s 0 0 2 8 1 6 ) b 7 b 0 t i m e r x c o u n t s o u r c e s e l e c t i o n b i t 0 : f ( x i n ) / 1 6 ( f ( x c i n ) / 1 6 i n l o w - s p e e d m o d e ? 0 w h e n r e a d ) t i m e r y o p e r a t i n g m o d e b i t s b 5 b 4 0 0 : t i m e r m o d e 0 1 : p e r i o d m e a s u r e m e n t m o d e 1 0 : e v e n t c o u n t e r m o d e 1 1 : p u l s e w i d t h h l c o n t i n u o u s l y m e a s u r e m e n t m o d e c n t r 1 a c t i v e e d g e s w i t c h b i t 0 : c o u n t a t r i s i n g e d g e i n e v e n t c o u n t e r m o d e m e a s u r e t h e f a l l i n g e d g e t o f a l l i n g e d g e p e r i o d i n p e r i o d m e a s u r e m e n t m o d e i n t e r r u p t f a l l i n g e d g e a c t i v e 1 : c o u n t a t f a l l i n g e d g e i n e v e n t c o u n t e r m o d e m e a s u r e t h e r i s i n g e d g e p e r i o d i n p e r i o d m e a s u r e m e n t m o d e i n t e r r u p t r i s i n g e d g e a c t i v e t i m e r y s t o p c o n t r o l b i t 0 : c o u n t s t a r t 1 : c o u n t s t o p ? 00 or 11 , the timer x count source is f(x cin )/16. when the timer x operating mode bits are 01 , the timer x count source is f(x cin ). 23 single-chip 8-bit cmos microcomputer mitsubishi microcomputers 38c8 group preliminar y notice: this is not a final specification. some parametric limits are subject to change. timer 1, timer 2, timer 3 timer 1, timer 2, and timer 3 are 8-bit timers. the count source for each timer can be selected by the timer 123 mode register. the timer latch value is not affected by a change of the count source. however, because changing the count source may cause an inadvertent count down of the timer. therefore, rewrite the value of timer whenever the count source is changed. timer 2 write control if the timer 2 write control bit is 0 , when the value is written in the address of timer 2, the value is loaded in the timer 2 and the latch at the same time. if the timer 2 write control bit is 1 , when the value is written in the address of timer 2, the value is loaded only in the latch. the value in the latch is loaded in timer 2 after timer 2 underflows. notes on timer 1 to timer 3 when the count source of timer 1 to 3 is changed, the timer counting value may be changed large because a thin pulse is generated in count input of timer. if timer 1 output is selected as the count source of timer 2 or timer 3, when timer 1 is written, the counting value of timer 2 or timer 3 may be changed large because a thin pulse is generated in timer 1 output. therefore, set the value of timer in the order of timer 1, timer 2 and timer 3 after the count source selection of timer 1 to 3. fig. 19 structure of timer 123 mode register t i m e r 1 2 3 m o d e r e g i s t e r ( t 1 2 3 m : a d d r e s s 0 0 2 9 1 6 ) * i n t e r n a l c l o c k 0 w h e n r e a d ) 24 single-chip 8-bit cmos microcomputer mitsubishi microcomputers 38c8 group preliminar y notice: this is not a final specification. some parametric limits are subject to change. serial i/o serial i/o can be used as either clock synchronous or asynchronous (uart) serial i/o. a dedicated timer (baud rate generator) is also provided for baud rate generation. (1) clock synchronous serial i/o mode clock synchronous serial i/o can be selected by setting the mode selection bit of the serial i/o control register to 1 . for clock synchronous serial i/o, the transmitter and the receiver must use the same clock. if an internal clock is used, transfer is started by a write signal to the transmit/receive buffer registers. fig. 20 block diagram of clock synchronous serial i/o fig. 21 operation of clock synchronous serial i/o function p 4 6 / s c l k p 4 7 / s r d y p 4 4 / r x d p 4 5 / t x d f ( x i n ) 1/4 1/4 f / f serial i/o status register s e r i a l i / o c o n t r o l r e g i s t e r r e c e i v e b u f f e r r e g i s t e r a d d r e s s 0 0 1 8 1 6 r e c e i v e s h i f t r e g i s t e r r e c e i v e b u f f e r f u l l f l a g ( r b f ) r e c e i v e i n t e r r u p t r e q u e s t ( r i ) clock control circuit s h i f t c l o c k s er i a l i / o clock selection bit frequency division ratio 1/(n+1) baud rate generator add ress 001 c 16 b r g c o u n t s o u r c e s e l e c t i o n b i t clock control circuit falling-edge detector d ata b us add ress 0018 16 s h i f t c l o c k t ransm i t s hif t reg i ster s hif t comp l et i on fl ag (tsc) t ransm i t b u ff er empty fl ag (tbe) t ransm i t i nterrupt request (ti) t r a n s m i t i n t e r r u p t s o u r c e s e l e c t i o n b i t add ress 0019 16 d ata b us a d d r e s s 0 0 1 a 1 6 transmit buffer register transmit shift register ( f ( x c i n ) i n l o w - s p e e d m o d e ) r e c e i v e e n a b l e s i g n a l s r d y d 7 d 0 d 1 d 2 d 3 d 4 d 5 d 6 rbf = 1 tsc = 1 t b e = 0 t b e = 1 t s c = 0 t ransm i t/rece i ve s hif t c l oc k (1/2 to 1/2048 of internal clock, or an external clock) s e r i a l o u t p u t t x d s e r i a l i n p u t r x d w r i t e s i g n a l t o r e c e i v e / t r a n s m i t b u f f e r r e g i s t e r ( a d d r e s s 0 0 1 8 1 6 ) o v e r r u n e r r o r ( o e ) d e t e c t i o n n otes 1: th e transm i t i nterrupt (ti) can b e se l ecte d to occur e i t h er w h en t h e transm i t b u ff er reg i ster h as empt i e d (tbe =1 ) or a f ter the transmit shift operation has ended (tsc=1), by setting the transmit interrupt source selection bit (tic) of the serial i/o control register. 2: if data is written to the transmit buffer register when tsc=0, the transmit clock is generated continuously and serial data is output continuously from the t x d pin. 3: the receive interrupt (ri) is set when the receive buffer full flag (rbf) becomes 1 . d 7 d 0 d 1 d 2 d 3 d 4 d 5 d 6 25 single-chip 8-bit cmos microcomputer mitsubishi microcomputers 38c8 group preliminar y notice: this is not a final specification. some parametric limits are subject to change. (2) asynchronous serial i/o (uart) mode clock asynchronous serial i/o mode (uart) can be selected by clear- ing the serial i/o mode selection bit of the serial i/o control register to 0 . eight serial data transfer formats can be selected, and the transfer formats used by a transmitter and receiver must be identical. the transmit and receive shift registers each have a buffer register, but the two buffers have the same address in memory. since the shift register cannot be written to or read from directly, transmit data is written to the transmit buffer, and receive data is read from the re- ceive buffer. the transmit buffer can also hold the next data to be transmitted, and the receive buffer register can hold a character while the next char- acter is being received. fig. 22 block diagram of uart serial i/o fig. 23 operation of uart serial i/o function f ( x i n ) 1 / 4 o e p e f e 1/16 1 / 1 6 d ata b us receive buffer register add ress 0018 16 r ece i ve s hif t reg i ster r e c e i v e b u f f e r f u l l f l a g ( r b f ) r e c e i v e i n t e r r u p t r e q u e s t ( r i ) b a u d r a t e g e n e r a t o r f r e q u e n c y d i v i s i o n r a t i o 1 / ( n + 1 ) a d d r e s s 0 0 1 c 1 6 st/sp/pa generator transmit buffer register d a t a b u s t ransm i t s hif t reg i ster a d d r e s s 0 0 1 8 1 6 t ransm i t s hif t reg i ster s hif t comp l et i on fl ag (tsc) t r a n s m i t b u f f e r e m p t y f l a g ( t b e ) t ransm i t i nterrupt request (ti) add ress 0019 16 s t d e t e c t o r s p d e t e c t o r uart contro l reg i ster a d d r e s s 0 0 1 b 1 6 c h a r a c t e r l e n g t h s e l e c t i o n b i t a d d r e s s 0 0 1 a 1 6 brg count source se l ect i on bi t t ransm i t i nterrupt source se l ect i on bit s e r i a l i / o c l o c k s e l e c t i o n b i t c l o c k c o n t r o l c i r c u i t c h a r a c t e r l e n g t h s e l e c t i o n b i t 7 b i t s 8 b i t s serial i/o control register p 4 6 / s clk s er i a l i / o status reg i ster p 4 4 / r x d p 4 5 / t x d t s c = 0 t b e = 1 r b f = 0 t b e = 0 tbe =0 rbf =1 r b f = 1 st d 0 d 1 s p d 0 d 1 s t s p t b e = 1 t s c = 1 ? ? n o t e s 1 : e r r o r f l a g d e t e c t i o n o c c u r s a t t h e s a m e t i m e t h a t t h e r b f f l a g b e c o m e s 1 ( a t 1 s t s t o p b i t , d u r i n g r e c e p t i o n ) . 2 : t h e t r a n s m i t i n t e r r u p t ( t i ) c a n b e s e l e c t e d t o o c c u r w h e n e i t h e r t h e t b e o r t s c f l a g b e c o m e s 1 b y t h e s e t t i n g o f t h e t r a n s m i t i n t e r r u p t s o u r c e s e l e c t i o n b i t ( t i c ) o f t h e s e r i a l i / o c o n t r o l r e g i s t e r . 3 : t h e r e c e i v e i n t e r r u p t ( r i ) i s s e t w h e n t h e r b f f l a g b e c o m e s 1 . 4 : a f t e r d a t a i s w r i t t e n t o t h e t r a n s m i t b u f f e r r e g i s t e r w h e n t s c = 1 , 0 . 5 t o 1 . 5 c y c l e s o f t h e d a t a s h i f t c y c l e i s n e c e s s a r y u n t i l c h a n g i n g t o t s c = 0 . 26 single-chip 8-bit cmos microcomputer mitsubishi microcomputers 38c8 group preliminar y notice: this is not a final specification. some parametric limits are subject to change. [transmit buffer/receive buffer register (tb/rb)] 0018 16 the transmit buffer register and the receive buffer register are lo- cated at the same address. the transmit buffer register is write-only and the receive buffer register is read-only. if a character bit length is 7 bits, the msb of data stored in the receive buffer register is 0 . [serial i/o status register (siosts)] 0019 16 the read-only serial i/o status register consists of seven flags (bits 0 to 6) which indicate the operating status of the serial i/o function and various errors. three of the flags (bits 4 to 6) are valid only in uart mode. the receive buffer full flag (bit 1) is cleared to 0 when the receive buffer is read. if there is an error, it is detected at the same time that data is trans- ferred from the receive shift register to the receive buffer register, and the receive buffer full flag is set. a write to the serial i/o status register clears all the error flags oe, pe, fe, and se. writing 0 to the serial i/o enable bit (sioe) also clears all the status flags, includ- ing the error flags. all bits of the serial i/o status register are initialized to 0 at reset, but if the transmit enable bit (bit 4) of the serial i/o control register has been set to 1 , the transmit shift register shift completion flag (bit 2) and the transmit buffer empty flag (bit 0) become 1 . [serial i/o control register (siocon)] 001a 16 the serial i/o control register contains eight control bits for the serial i/o1 function. [uart control register (uartcon) ]001b 16 this is a 5 bit register containing four control bits, which are valid when uart is selected and set the data format of an data receiver/ transfer, and one control bit, which is always valid and sets the out- put structure of the p4 5 /t x d pin. [baud rate generator(brg)] 0016 16 the baud rate generator determines the baud rate for serial transfer. the baud rate generator divides the frequency of the count source by 1/(n + 1), where n is the value written to the baud rate generator. notes on serial i/o when setting the transmit enable bit to 1 , the serial i/o transmit interrupt request bit is automatically set to 1 . when not requiring the interrupt occurrence synchronized with the transmission enalbed, take the following sequence. ? 0 (disabled). ? 1 . ? 0 after 1 or more instructions have been executed. ? 1 (enabled). 27 single-chip 8-bit cmos microcomputer mitsubishi microcomputers 38c8 group preliminar y notice: this is not a final specification. some parametric limits are subject to change. fig. 24 structure of serial i/o control registers brg count source se l ect i on bi t (css) 0: f(x in ) (f(x cin ) in low-speed mode) 1: f(x in )/4 (f(x cin )/4 in low-speed mode) serial i/o synchronous clock selection bit (scs) 0: brg output divided by 4 when clock synchronous serial i/o is selected. brg output divided by 16 when uart is selected. 1: external clock input when clock synchronous serial i/o is selected. external clock input divided by 16 when uart is selected. s rdy output enable bit (srdy) 0: p4 7 pin operates as ordinary i/o pin. 1: p4 7 pin operates as s rdy output pin. transmit interrupt source selection bit (tic) 0: interrupt when transmit buffer has emptied 1: interrupt when transmit shift operation is completed transmit enable bit (te) 0: transmit disabled 1: transmit enabled receive enable bit (re) 0: receive disabled 1: receive enabled serial i/o mode selection bit (siom) 0: asynchronous serial i/o (uart) 1: clock synchronous serial i/o serial i/o enable bit (sioe) 0: serial i/o disabled (pins p4 4 C p4 7 operate as ordinary i/o pins) 1: serial i/o enabled (pins p4 4 C p4 7 operate as serial i/o pins) s er i a l i / o contro l reg i ster (siocon : address 001a 16 ) b 7b 0 t r a n s m i t b u f f e r e m p t y f l a g ( t b e ) 0 : b u f f e r f u l l 1 : b u f f e r e m p t y r e c e i v e b u f f e r f u l l f l a g ( r b f ) 0 : b u f f e r e m p t y 1 : b u f f e r f u l l t r a n s m i t s h i f t r e g i s t e r s h i f t c o m p l e t i o n f l a g ( t s c ) 0 : t r a n s m i t s h i f t i n p r o g r e s s 1 : t r a n s m i t s h i f t c o m p l e t e d o v e r r u n e r r o r f l a g ( o e ) 0 : n o e r r o r 1 : o v e r r u n e r r o r p a r i t y e r r o r f l a g ( p e ) 0 : n o e r r o r 1 : p a r i t y e r r o r f r a m i n g e r r o r f l a g ( f e ) 0 : n o e r r o r 1 : f r a m i n g e r r o r s u m m i n g e r r o r f l a g ( s e ) 0 : o e u p e u f e = 0 1 : o e u p e u f e = 1 n o t u s e d ( r e t u r n s 1 w h e n r e a d ) s e r i a l i / o s t a t u s r e g i s t e r ( s i o s t s : a d d r e s s 0 0 1 9 1 6 ) b 7b 0 u a r t c o n t r o l r e g i s t e r ( u a r t c o n : a d d r e s s 0 0 1 b 1 6 ) c h a r a c t e r l e n g t h s e l e c t i o n b i t ( c h a s ) 0 : 8 b i t s 1 : 7 b i t s p a r i t y e n a b l e b i t ( p a r e ) 0 : p a r i t y c h e c k i n g d i s a b l e d 1 : p a r i t y c h e c k i n g e n a b l e d p a r i t y s e l e c t i o n b i t ( p a r s ) 0 : e v e n p a r i t y 1 : o d d p a r i t y s t o p b i t l e n g t h s e l e c t i o n b i t ( s t p s ) 0 : 1 s t o p b i t 1 : 2 s t o p b i t s p 4 5 / t x d p - c h a n n e l o u t p u t d i s a b l e b i t ( p o f f ) 0 : c m o s o u t p u t ( i n o u t p u t m o d e ) 1 : n - c h a n n e l o p e n - d r a i n o u t p u t ( i n o u t p u t m o d e ) n o t u s e d ( r e t u r n 1 w h e n r e a d ) b 7b 0 28 single-chip 8-bit cmos microcomputer mitsubishi microcomputers 38c8 group preliminar y notice: this is not a final specification. some parametric limits are subject to change. a-d converter [a-d conversion registers (adl, adh)] 0032 16 , 0033 16 the a-d conversion registers are read-only registers that contain the result of an a-d conversion. during a-d conversion, do not read these registers. [a-d control register (adcon)] 0031 16 the a-d control register controls the a-d conversion process. bits 0 to 2 are analog input pin selection bits. bit 3 is an a-d conversion completion bit and 0 during a-d conversion, then changes to 1 when the a-d conversion is completed. writing 0 to this bit starts the a-d conversion. when bit 5, which is the ad external trigger valid bit, is set to 1 , a-d conversion is started even by a rising edge or falling edge of an adt input. comparator and control circuit the comparator and control circuit compares an analog input volt- age with the comparison voltage and stores the result in the a-d conversion register. when an a-d conversion is completed, the con- trol circuit sets the ad conversion completion bit and the ad interrupt request bit to 1 . because the comparator consists of a capacitor coupling, a deficient conversion speed may cause lack of electric charge and make the conversion accuracy worse. when a-d conversion is performed in the middle-speed mode or the high-speed mode, set f(x in ) to at least 500 khz. in the low-speed mode, a-d conversion is performed by using the built-in self-oscillation circuit. therefore, there is no limitation in the lower bound frequency of f(x in ). trigger start when using the a-d external trigger, set the port shared with the adt pin to input. the polarity of int1 interrupt edge also applies to the a-d external trigger. when the int1 interrupt edge polarity is switched after an external trigger is validated, an a-d conversion may be started. fig. 26 a-d converter block diagram fig. 25 structure of a-d control register resistor ladder the resistor ladder outputs the comparison voltage by dividing the voltage between v dd and v ss by resistance. channel selector the channel selector selects one of the ports p3 3 /a in3 C p3 0 /a in0 and ports p1 0 /a in4 C p1 3 /a in7 , and inputs it to the comparator. a - d c o n t r o l r e g i s t e r ( a d c o n : a d d r e s s 0 0 3 1 1 6 ) a n a l o g i n p u t p i n s e l e c t i o n b i t s 0 0 0 : p 3 0 / a i n 0 0 0 1 : p 3 1 / a i n1 0 1 0 : p 3 2 / a i n2 0 1 1 : p 3 3 / a i n3 1 0 0 : p 1 0 / a i n4 1 0 1 : p 1 1 / a i n5 1 1 0 : p 1 2 / a i n6 1 1 1 : p 1 3 / a i n7 b 7 b 0 b 7 b 9 b 8 b 7 b 6 b 5 b 4 b 3 b 2 b 9 b 8 b 7 b 6 b 5 b 4 b 3 b 2 ? 8-bit read (read only address 0032 16 .) a - d c o n v e r s i o n r e g i s t e r ( l o w - o r d e r ) ( a d l : a d d r e s s 0 0 3 2 1 6 ) ? 1 0 - b i t r e a d ( r e a d a d d r e s s 0 0 3 3 1 6 f i r s t . ) n o t e : h i g h - o r d e r 6 b i t s o f a d d r e s s 0 0 3 3 1 6 b e c o m e s 0 a t r e a d i n g . b 1 b 0 b 0 a - d convers i on reg i ster (l ow-or d er ) (adl: address 0032 16 ) a - d c o n v e r s i o n r e g i s t e r ( h i g h - o r d e r ) ( a d h : a d d r e s s 0 0 3 3 1 6 ) b 7 b 0 b 7 b 0 ad convers i on comp l et i on bi t 0 : conversion in progress 1 : conversion completed n o t u s e d ( r e t u r n 0 w h e n r e a d ) a d e x t e r n a l t r i g g e r v a l i d b i t 0 : a - d e x t e r n a l t r i g g e r i n v a l i d 1 : a - d e x t e r n a l t r i g g e r v a l i d n o t u s e d ( r e t u r n 0 w h e n r e a d ) a-d control circuit v s s b 7 b0 3 p 3 0 / a i n 0 p 3 1 / a i n1 p 3 2 / a i n2 p 3 3 / a i n3 p 1 0 / a i n4 p 1 1 / a i n5 p 1 2 / a i n6 p 1 3 / a i n7 1 0 p4 1 /int 1 /adt ( h ) (l) v c c d a t a b u s a - d c o n t r o l r e g i s t e r a-d conversion register resistor ladder comparater a-d interrupt request c h a n n e l s e l e c t o r a-d conversion register 29 single-chip 8-bit cmos microcomputer mitsubishi microcomputers 38c8 group preliminar y notice: this is not a final specification. some parametric limits are subject to change. lcd controller/driver the 38c8 group has the built-in liquid crystal display (lcd) controller/driver consisting of the following. 240-byte lcd display ram 52 or 68 segment driver 16 or 32 common driver lcd clock generator timing controller bias controller voltage multiplier lcd mode register lcd control registers 1, 2 a maximum of 68 segment output pins and 32 common output pins can be used for control of external lcd display. fig. 27 block diagram of lcd controller/driver l c d c k l c d c l o c k g e n e r a t o r s e g 8 s e g 9 s e g 5 8 s e g 5 9 178 1 41 5 0 c o m 3 1 / s e g 6 0 c o m 1 7 / s e g 1 1 3 3 8 4 1 3 4 8 3 c o m 0c o m 1 6 5 c o m 1 5 7 4 7 3 1 4 1 c o m 1 6 / s e g 0 1 4 2 l m 1l m 0 l m 7l m 2 l m 3 l m 4 l m 5 l m 6 1781 41 5 0 1781 41 5 0 1781 41 5 0 1 0 f ( x i n ) / 1 0 2 4 f ( x c i n ) / 1 6 0 0 4 0 1 6 , 0 0 8 4 1 6 o r 0 3 4 0 1 6 , 0 3 8 4 1 6 b i t 0 0 4 1 1 6 , 0 0 8 5 1 6 o r 0 3 4 1 1 6 , 0 3 8 5 1 6 b i t 0 0 8 2 1 6 , 0 0 c 6 1 6 o r 0 3 8 2 1 6 , 0 3 c 6 1 6 b i t 0 0 8 3 1 6 , 0 0 c 7 1 6 o r 0 3 8 3 1 6 , 0 3 c 7 1 6 b i t l c 1 1l c 1 0 l c 1 7l c 1 2 l c 1 3 l c 1 4 l c 1 6l c 1 5 b i t s e l e c t o r c o m m o n / s e g m e n t d r i v e r l c 2 1l c 2 0 l c 2 7l c 2 2 l c 2 3 l c 2 4 l c 2 6l c 2 5 7 8 9 1 0 1 1 v l 1 v l 2 v l 3 v l 4 v l 5 1 4 c 1 1 3 c 2 1 2 c 3 v l i n 1 5 l c d d i s p l a y r a m d a t a b u s l c d m o d e r e g i s t e r ( a d d r e s s 0 0 3 9 1 6 ) l c d c o n t r o l r e g i s t e r 1 ( a d d r e s s 0 0 3 7 1 6 ) l c d c o n t r o l r e g i s t e r 2 ( a d d r e s s 0 0 3 8 1 6 ) t i m i n g c o n t r o l l e r c o m m o n d r i v e r v o l t a g e m u l t i p l i e r b i a s c o n t r o l l e r s e g m e n t d r i v e r s e g m e n t d r i v e r s e g m e n t d r i v e r s e g m e n t d r i v e r b i t s e l e c t o rb i t s e l e c t o rb i t s e l e c t o r 30 single-chip 8-bit cmos microcomputer mitsubishi microcomputers 38c8 group preliminar y notice: this is not a final specification. some parametric limits are subject to change. fig. 28 structure of lcd control register table 7 maximum number of display pixels at each duty ratio duty ratio maximum number of display pixel 16 ? ? ? ? lcd controller/driver function the controller/driver performs the bias control and the time sharing control by the lcd control registers 1, 2 (lc1, lc2), and the lcd mode register (lm). the data of corresponding lcdram is output from the segment pins according to the output timing of the common pins. the 38c8 group has the voltage multiplier only for lcd in addition to lcd controller/driver . [lcd mode register (lm)] 0039 16 the lcd mode register is used for setting the lcd controller/driver according to the lcd panel used. [lcd control register 1 (lc1)] 0037 16 the lcd control register 1 controls the voltage multiplier and built-in resistance. [lcd control register 2 (lc2)] 0038 16 the lcd control register 2 is read-only. setting 1 to bit 5 makes built-in resistance low resistance, and can raise drivability of the seg- ment pins and the common pins. note: when executing the stp instruction while operating lcd, ex- ecute the stp instruction after prohibiting lcd (set 0 to bit 3 of the lcd mode regsiter). lcd control register 1 (lc1: address 0037 16 ) b 7b0 n o t e 1 : c o n s u m p t i o n c u r r e n t c a n b e r e d u c e d b y r e s t r a i n t o f d r i v a b i l i t y . b u t a n i r r e g u l a r d i s p l a y m i g h t b e c a u s e d a c c o r d i n g t o t h e p a n e l o r t h e d i s p l a y p a t t e r n . n o t u s e d ( d o n o t w r i t e 1 t o t h e s e b i t s . ) b7 b0 n o t e 2 : t h e d r i v e o f a m o r e l a r g e - s c a l e l c d p a n e l b e c o m e s e a s y b y s e t t i n g 1 t o t h i s b i t . b u t c o n s u m p t i o n c u r r e n t i s i n c r e a s e d a t l c d d r i v e . w h e n t h e d r i v a b i l i t y s e l e c t i o n b i t 1 i s 1 , t h i s f u n c t i o n i s i n v a i d . b 7b 0 note 3: lcdck is a clock for a lcd timing controller. internal clock ? 1 t o t h e s e b i t s . ) duty ratio selsection bit ? C com 31 ) 0 : 16 duty (use com 0 C com 15 ) not used (do not write 0 to this bit.) lcd display ram address selection bit 0 : 3 page 1 : 0 page lcd enable bit 0 : lcd off 1 : lcd on lcd drive timing selection bit 0 : a type 1 : b type lcdck division ratio selection bits b6 b5 0 0 : clock input 0 1 : 2 division of clock input 1 0 : 4 division of clock input 1 1 : 8 division of clock input lcdck count source selection bit (note 3) 0 : f(x in )/1024 1 : f(x cin )/16 l c d m o d e r e g i s t e r ( l m : a d d r e s s 0 0 3 9 1 6 ) v o l t a g e m u l t i p l i e r e n a b l e b i t 0 : v o l t a g e m u l t i p l i e r s t o p 1 : v o l t a g e m u l t i p l i e r o p e r a t i n g n o t u s e d ( d o n o t w r i t e 1 t o t h i s b i t . ) drivability selection bit 1 0 : normal (drivability selection bit 2 valid) 1 : restraint ( note 1) lcd control register 2 (lc2: address 0038 16 ) n o t u s e d ( d o n o t w r i t e 1 t o t h e s e b i t s . ) d r i v a b i l i t y s e l e c t i o n b i t 2 0 : n o r m a l 1 : r e i n f o r c i n g ( n o t e 2 ) 31 single-chip 8-bit cmos microcomputer mitsubishi microcomputers 38c8 group preliminar y notice: this is not a final specification. some parametric limits are subject to change. voltage multiplier when the voltage multiplier is operated after a reference voltage for boosting is applied to lcd power supply v lin , a voltage that is three times as large as v lin pin occurs at the v l5 pin. operate the voltage multiplier after applying a reference voltage for boosting to v lin . bias control in the lcd power source pins (v l1 C v l5 ), a proper level is automati- cally generated in 1/32 and 1/16 duty ratio. the quality of the lcd display can be stabilized by connecting the capacitor for smooth- ness between vss and these pins. fig. 29 example of circuit at each bias table 8 bias control and applied voltage to v l1 ? l5 bias value voltage value v l5 = v lcd v l4 = 6/7 v lcd v l3 = 5/7 v lcd v l2 = 2/7 v lcd v l1 = 1/7 v lcd v l5 = v lcd v l4 = 4/5 v lcd v l3 = 3/5 v lcd v l2 = 2/5 v lcd v l1 = 1/5 v lcd note: v lcd is a value which can be supplied to the lcd panel. set value which is less than maximum ratings to v lcd . 1/5 bias 1/7 bias ? at 1/5 bias r1=r2=r3=r4=r5 ? at 1/7 bias r1=r2=r4=r5 r3=3 ? r1 v l 5 v l4 v l3 v l2 v l1 c 3 c 2 c 1 v lin r 1 r2 v l 5 v l4 v l3 v l2 v l1 r 3 r 4 r 5 r t c 3 c 2 c 1 v lin v l5 v l 4 v l3 v l2 v l1 r t c 3 c 2 c 1 v lin 1 / 5 , 1 / 7 b i a s w h e n u s i n g v o l t a g e m u l t i p l i e r c i r c u i t 1 / 5 , 1 / 7 b i a s wh e n n o t u s i n g v o l t a g e m u l t i p l i e r c i r c u i t ( 1 ) 1/5, 1/7 bias when not using voltage multiplier circuit (2) 1.3 to 2.33 v 32 single-chip 8-bit cmos microcomputer mitsubishi microcomputers 38c8 group preliminar y notice: this is not a final specification. some parametric limits are subject to change. common pin and duty ratio control the common pins (com 0 C com 31 ) to be used are determined by duty ratio. select duty ratio by the duty ratio selection bit (bit 0 of the lcd mode register). table 9 duty ratio control and common pins used duty ratio common pins used note: the seg 0 /com 16 C seg 7 /com 23 pins are used as the seg 0 C seg 7 . the seg 67 /com 24 C seg 60 /com 31 pins are used as the seg 67 C seg 60 . com 0 C com 15 (note) duty ratio selection bit 16 32 0 1 com 0 C com 31 lcd display ram addresses 0040 16 to 012f 16 is the designated ram for the lcd display. when 1 are written to these addresses, the corresponding segments of the lcd display panel are turned on. fig. 30 lcd display ram map (frequency of count source for lcdck) (divider division ratio for lcd) f(lcdck) (duty ratio) lcd drive timing the lcdck timing frequency (lcd drive timing) is generated inter- nally and the frame frequency can be determined with the following equation; f(lcdck) = frame frequency = s e g 0 s e g 1 s e g 2 s e g 3 s e g 4 s e g 5 s e g 6 s e g 7 s e g 8 s e g 9 s e g 1 0 s e g 1 1 s e g 1 2 s e g 1 3 s e g 1 4 s e g 1 5 s e g 1 6 s e g 1 7 s e g 1 8 s e g 1 9 s e g 2 0 s e g 2 1 s e g 2 2 s e g 2 3 s e g 4 4 s e g 4 5 s e g 4 6 s e g 4 7 s e g 4 8 s e g 4 9 s e g 5 0 s e g 5 1 s e g 5 2 s e g 5 3 s e g 5 4 s e g 5 5 s e g 5 6 s e g 5 7 s e g 5 8 s e g 5 9 s e g 6 0 s e g 6 1 s e g 6 2 s e g 6 3 s e g 6 4 s e g 6 5 s e g 6 6 s e g 6 7 000000001000101110111110 001110010001011100000000lsb 000000001101100100001000 01000 010001001000000000 000000001010100100001000 010000010001001000000000 000000001000100100001000 001110011111001000000000 000000001000100100001000 000001010001001000000000 000000001000100100001000 010001010001001000000000 000000001000101110001000 001110010001011100000000 000000000000000000000000 000000000000000000000000msb 010001011111001110001110 111110111110111110111100lsb 011011000010010001010001 100000100000100000100010 010101000100010001010000 100000100000100000100010 010001000010001110010000 111100111100111100111100 010001000001010001010000 100000100000100000100000 010001010001010001010001 100000100000100000100000 010001001110001110001110 111110100000100000100000 000000000000000000000000 000000000000000000000000m s b 0010001011111001 1001000101111100l s b 0011011000010010 0101101101000000 0010101000100010 0101010101000000 0010001000010001 1101000101111000 0010001000001010 0101000101000000 0010001010001010 0101000101000000 0010001001110001 001000101000000 com0 com1 c o m 2 c o m 3 c o m 4 c o m 5 c o m 6 com7 c o m 1 7 c o m 1 8 c o m 1 9 c o m 2 0 com21 com22 com23 0000000000000000 0000000000000000msb 0000000000100010 1111101111000000lsb 0000000000100010 1000001000100000 0000000000010100 1000001000100000 0000001110001000 1111001111000000 0000000000010100 1000001000000000 0000000000100010 1000001000000000 0000000000100010 1000001000000000 com8 com9 com10 com11 c o m 1 2 c o m 1 3 c o m 1 4 c o m 1 5 com24 com25 com26 com27 c o m 2 8 c o m 2 9 c o m 3 0 c o m 3 1 0000000000000000 0000000000000000m s b l c d d i s p l a y m a p w h e n s e l e c t i n g 3 p a g e 0 3 4 0 0 3 4 1 0 3 4 2 0 3 4 3 0 3 4 4 0 3 4 5 0 3 4 6 0 3 4 7 0 3 4 8 0 3 4 9 0 3 4 a 0 3 4 b 0 3 4 c 0 3 4 d 0 3 4 e 0 3 4 f 0 3 5 0 0 3 5 1 0 3 5 2 0 3 5 3 0 3 5 4 0 3 5 5 0 3 5 6 0 3 5 7 0 3 6 c 0 3 6 d 0 3 6 e 0 3 6 f 0 3 7 0 0 3 7 1 0 3 7 2 0 3 7 8 0 3 7 4 0 3 7 5 0 3 7 6 0 3 7 7 0 3 7 8 0 3 7 9 0 3 7 a 0 3 7 b 0 3 7 c 0 3 7 d 0 3 7 e 0 3 7 f 0 3 8 0 0 3 8 1 0 3 8 2 0 3 8 3 0 3 8 4 0 3 8 5 0 3 8 6 0 3 8 7 0 3 8 8 0 3 8 9 0 3 8 a 0 3 8 b 0 3 8 c 0 3 8 d 0 3 8 e 0 3 8 f 0 3 9 0 0 3 9 1 0 3 9 2 0 3 9 3 0 3 9 4 0 3 9 5 0 3 9 6 0 3 9 7 0 3 9 8 0 3 9 9 0 3 9 a 0 3 9 b 0 3 b 0 0 3 b 1 0 3 b 2 0 3 b 3 0 3 b 4 0 3 b 5 0 3 b 6 0 3 b 7 0 3 b 8 0 3 b 9 0 3 b a 0 3 b b 0 3 b c 0 3 b d 0 3 b e 0 3 b f 0 3 c 0 0 3 c 1 0 3 c 2 0 3 c 3 0 3 c 4 0 3 c 5 0 3 c 6 0 3 c 7 0 3 c 8 0 3 c 9 0 3 c a 0 3 c b 0 3 c c 0 3 c d 0 3 c e 0 3 c f 0 3 d 0 0 3 d 1 0 3 d 2 0 3 d 3 0 3 d 4 0 3 d 5 0 3 d 6 0 3 d 7 0 3 e c 0 3 e d 0 3 e e 0 3 e f 0 3 f 0 0 3 f 1 0 3 f 2 0 3 f 3 0 3 f 4 0 3 f 5 0 3 f 6 0 3 f 7 0 3 f 8 0 3 f 9 0 3 f a 0 3 f b 0 3 f c 0 3 f d 0 3 f e 0 3 f f 0 4 0 0 0 4 0 1 0 4 0 2 0 4 0 3 0 4 0 4 0 4 0 5 0 4 0 6 0 4 0 7 0 4 0 8 0 4 0 9 0 4 0 a 0 4 0 b 0 4 2 0 0 4 2 1 0 4 2 2 0 4 2 3 0 4 2 4 0 4 2 5 0 4 2 6 0 4 2 7 0 4 2 8 0 4 2 9 0 4 2 a 0 4 2 b 0 4 2 c 0 4 2 d 0 4 2 e 0 4 2 f 0 0 4 0 0 0 4 1 0 0 4 2 0 0 4 3 0 0 4 4 0 0 4 5 0 0 4 6 0 0 4 7 0 0 4 8 0 0 4 9 0 0 4 a 0 0 4 b 0 0 4 c 0 0 4 d 0 0 4 e 0 0 4 f 0 0 5 0 0 0 5 1 0 0 5 2 0 0 5 3 0 0 5 4 0 0 5 5 0 0 5 6 0 0 5 7 0 0 6 c 0 0 6 d 0 0 6 e 0 0 6 f 0 0 7 0 0 0 7 1 0 0 7 2 0 0 7 3 0 0 7 4 0 0 7 5 0 0 7 6 0 0 7 7 0 0 7 8 0 0 7 9 0 0 7 a 0 0 7 b 0 0 7 c 0 0 7 d 0 0 7 e 0 0 7 f 0 0 8 0 0 0 8 1 0 0 8 2 0 0 8 3 0 0 8 4 0 0 8 5 0 0 8 6 0 0 8 7 0 0 8 8 0 0 8 9 0 0 8 a 0 0 8 b 0 0 8 c 0 0 8 d 0 0 8 e 0 0 8 f 0 0 9 0 0 0 9 1 0 0 9 2 0 0 9 3 0 0 9 4 0 0 9 5 0 0 9 6 0 0 9 7 0 0 9 8 0 0 9 9 0 0 9 a 0 0 9 b 0 0 b 0 0 0 b 1 0 0 b 2 0 0 b 3 0 0 b 4 0 0 b 5 0 0 b 6 0 0 b 7 0 0 b 8 0 0 b 9 0 0 b a 0 0 b b 0 0 b c 0 0 b d 0 0 b e 0 0 b f 0 0 c 0 0 0 c 1 0 0 c 2 0 0 c 3 0 0 c 4 0 0 c 5 0 0 c 6 0 0 c 7 0 0 d 6 0 0 c 8 0 0 c 9 0 0 c a 0 0 c b 0 0 c c 0 0 c d 0 0 c e 0 0 c f 0 0 d 0 0 0 d 1 0 0 d 2 0 0 d 3 0 0 d 4 0 0 d 5 0 0 d 7 0 0 e c 0 0 e d 0 0 e e 0 0 e f 0 0 f 0 0 0 f 1 0 0 f 2 0 0 f 3 0 0 f 4 0 0 f 5 0 0 f 6 0 0 f 7 0 0 f 8 0 0 f 9 0 0 f a 0 0 f b 0 0 f c 0 0 f d 0 0 f e 0 0 f f 0 1 0 0 0 1 0 1 0 1 0 2 0 1 0 3 0 1 0 4 0 1 0 5 0 1 0 6 0 1 0 7 0 1 0 8 0 1 0 9 0 1 0 a 0 1 0 b 0 1 2 0 0 1 2 1 0 1 2 2 0 1 2 3 0 1 2 4 0 1 2 5 0 1 2 6 0 1 2 7 0 1 2 8 0 1 2 9 0 1 2 a 0 1 2 b 0 1 2 c 0 1 2 d 0 1 2 e 0 1 2 f 1 1 c o m 1 6 when selecting 0 page 33 single-chip 8-bit cmos microcomputer mitsubishi microcomputers 38c8 group preliminar y notice: this is not a final specification. some parametric limits are subject to change. fig. 31 lcd drive waveform (1/16 duty ratio, 1/5 bias, a type) s e g 0 C c o m 2 3 s e g 0 C c o m 2 2 l c d c k c o m 2 3 v l 5 v l 4 v l 3 v l 2 v l 1 v s s c o m 2 2 v l 5 v l 4 v l 3 v l 2 v l 1 v s s v l 5 v l 4 v l 3 v l 2 v l 1 v s s v l 1 v l 2 v l 3 v l 4 v l 5 seg 0 v l 5 v l 4 v l 3 v l 2 v l 1 v s s v l 5 v l 4 v l 3 v l 2 v l 1 v s s v l 1 v l 2 v l 3 v l 4 v l 5 1 f r a m e ( 1 6 c l o c k s ) o f f o f f o n 1 f rame ( 16 c l oc k s ) off off on 34 single-chip 8-bit cmos microcomputer mitsubishi microcomputers 38c8 group preliminar y notice: this is not a final specification. some parametric limits are subject to change. fig. 32 lcd drive waveform (1/32 duty ratio, 1/7 bias, b type) lcdck c o m 3 0 seg 0 C com 31 s e g 0 v l5 v l4 v l3 v l2 v l1 v ss v l 5 v l 4 v l 3 v l 2 v l 1 v s s v l 5 v l 4 v l 3 v l 2 v l 1 v s s v l 1 v l 2 v l 3 v l 4 v l 5 o f f o n off o n o f f on seg 0 C com 30 v l5 v l4 v l3 v l2 v l1 v ss v l1 v l2 v l3 v l4 v l5 o f f o f f off c o m 3 1 v l5 v l4 v l3 v l2 v l1 v ss 1 f r a m e ( 3 2 c l o c k s ) 1 f r a m e ( 3 2 c l o c k s ) 35 single-chip 8-bit cmos microcomputer mitsubishi microcomputers 38c8 group preliminar y notice: this is not a final specification. some parametric limits are subject to change. reset circuit to reset the microcomputer, reset pin should be held at an l level for 2 s or more. then the reset pin is returned to an h level (the power source voltage should be between v cc (min.) and 5.5 v, and the quartz-crystal oscillator should be stable), reset is released. after the reset is completed, the program starts from the address contained in address fffd 16 (high-order byte) and address fffc 16 (low-order byte). make sure that the reset input voltage is less than 0.2vcc when a power source voltage passes v cc (min.). fig. 34 reset sequence fig. 33 reset circuit example ( n o t e ) 0 . 2 v c c 0 v 0 v p o w e r o n v c c r e s e t v c c r e s e t p o w e r s o u r c e v o l t a g e d e t e c t i o n c i r c u i t p o w e r s o u r c e v o l t a g e r e s e t i n p u t v o l t a g e note : reset release voltage ; v cc =3.0 v. r e s e t i n t e r n a l r e s e t a d d r e s s d a t a s y n c x i n f f f cf f f d a d h , a d l a d l a d h ???? x i n : a b o u t 8 2 0 0 c y c l e s n o t e s 1 : t h e f r e q u e n c y r e l a t i o n o f f ( x i n ) a n d f ( ) i s f ( x i n ) = 8 ? f ( ) . 2 : t h e q u e s t i o n m a r k s ( ? ) i n d i c a t e a n u n d e f i n e d s t a t e t h a t d e p e n d s o n t h e p r e v i o u s s t a t e . r e s e t a d d r e s s f r o m v e c t o r t a b l e 36 single-chip 8-bit cmos microcomputer mitsubishi microcomputers 38c8 group preliminar y notice: this is not a final specification. some parametric limits are subject to change. fig. 35 internal status at reset ? ? ? ? ? ? ? 1 a d d r e s s ( 2 1 ) ( 2 2 ) ( 2 3 ) ( 2 4 ) ( 2 5 ) ( 2 6 ) ( 2 7 ) ( 2 8 ) ( 2 9 ) ( 3 0 ) ( 3 1 ) ( 3 2 ) ( 3 3 ) ( 3 4 ) ( 1 ) ( 2 ) ( 3 ) ( 4 ) ( 5 ) ( 6 ) ( 7 ) ( 8 ) ( 9 ) ( 1 0 ) ( 1 1 ) ( 1 2 ) ( 1 3 ) ( 1 4 ) ( 1 5 ) ( 1 6 ) ( 1 7 ) ( 1 8 ) ( 1 9 ) ( 2 0 ) p o r t p 0 d i r e c t i o n r e g i s t e r p o r t p 1 d i r e c t i o n r e g i s t e r p o r t p 2 d i r e c t i o n r e g i s t e r p o r t p 3 d i r e c t i o n r e g i s t e r p o r t p 4 d i r e c t i o n r e g i s t e r p u l l r e g i s t e r a p u l l r e g i s t e r b s e r i a l i / o s t a t u s r e g i s t e r s e r i a l i / o c o n t r o l r e g i s t e r u a r t c o n t r o l r e g i s t e r t i m e r x ( l o w - o r d e r ) t i m e r x ( h i g h - o r d e r ) t i m e r y ( l o w - o r d e r ) t i m e r y ( h i g h - o r d e r ) t i m e r 1 t i m e r 2 t i m e r 3 t i m e r x m o d e r e g i s t e r t i m e r y m o d e r e g i s t e r t i m e r 1 2 3 m o d e r e g i s t e r 0 0 0 1 1 6 0 0 0 3 1 6 0 0 0 5 1 6 0 0 0 7 1 6 0 0 0 9 1 6 0 0 1 6 1 6 0 0 1 7 1 6 0 0 1 9 1 6 0 0 1 a 1 6 0 0 1 b 1 6 0 0 2 0 1 6 0 0 2 1 1 6 0 0 2 2 1 6 0 0 2 3 1 6 0 0 2 4 1 6 0 0 2 5 1 6 0 0 2 6 1 6 0 0 2 7 1 6 0 0 2 8 1 6 0 0 2 9 1 6 r e g i s t e r c o n t e n t s a d d r e s s note: the contents of all other register and ram are undefined after reset, so they must be initialized by software. ? : undefined register contents 0 0 1 6 0 0 1 6 0 0 1 6 0 0 1 6 0 0 1 6 0 0 1 6 0 0 1 6 80 1 6 0 0 1 6 e 0 1 6 f f 1 6 f f 1 6 f f 1 6 f f 1 6 f f 1 6 0 1 1 6 f f 1 6 0 0 1 6 0 0 1 6 0 0 1 6 0 0 3 1 1 6 0 0 3 2 1 6 0 0 3 3 1 6 0 0 3 7 1 6 0 0 3 8 1 6 0 0 3 9 1 6 0 0 3 a 1 6 0 0 3 b 1 6 0 0 3 c 1 6 0 0 3 d 1 6 0 0 3 e 1 6 0 0 3 f 1 6 ( p s ) ( p c h ) ( p c l ) a - d c o n t r o l r e g i s t e r a - d c o n v e r s i o n r e g i s t e r ( l o w - o r d e r ) a - d c o n v e r s i o n r e g i s t e r ( h i g h - o r d e r ) l c d c o n t r o l r e g i s t e r 1 l c d c o n t r o l r e g i s t e r 2 l c d m o d e r e g i s t e r i n t e r r u p t e d g e s e l e c t i o n r e g i s t e r c p u m o d e r e g i s t e r i n t e r r u p t r e q u e s t r e g i s t e r 1 i n t e r r u p t r e q u e s t r e g i s t e r 2 i n t e r r u p t c o n t r o l r e g i s t e r 1 i n t e r r u p t c o n t r o l r e g i s t e r 2 p r o c e s s o r s t a t u s r e g i s t e r p r o g r a m c o u n t e r c o n t e n t s o f a d d r e s s f f f d 1 6 c o n t e n t s o f a d d r e s s f f f c 1 6 0 8 1 6 x x 1 6 x x 1 6 0 0 1 6 0 0 1 6 0 3 1 6 0 0 1 6 4 c 1 6 0 0 1 6 0 0 1 6 0 0 1 6 0 0 1 6 37 single-chip 8-bit cmos microcomputer mitsubishi microcomputers 38c8 group preliminar y notice: this is not a final specification. some parametric limits are subject to change. clock generating circuit the 38c8 group has two built-in oscillation circuits. an oscillation circuit can be formed by connecting a resonator between x in and x out (x cin and x cout ). rc oscillation is available for x in -x out . immediately after power on, only the x in oscillation circuit starts os- cillating, and x cin and x cout pins go to high impedance state. main clock an oscillation circuit by a resonator can be formed by setting the oscsel pin is set to l level and connecting a resonator between x in and x out. use the circuit constants in accordance with the reso- nator manufacturer s recommended values. no external resistor is needed between x in and x out since a feed-back resistor exists on- chip. to supply a clock signal externally, make the x out pin open in the l level state of the oscsel pin, and supply the clock from the x in pin. the rc oscillation circuit can be formed by setting the oscsel pin to h level and connecting a resistor between the x in pin and the x out pin. at this time, the feed-back resistor is cut off. the frequency of the rc oscillation changes owing to a parasitic capacitance or the wiring length etc. of the printed circuit board. do not use the rc oscillation in the usage which the frequency accuracy of the main clock is needed. sub-clock connect a resonator between x cin and x cout . an external feed- back resistor is needed between x cin and x cout since a feed-back resistor does not exist on-chip. the sub-clock x cin -x cout oscillation circuit cannot directly input clocks that are externally generated. ac- cordingly, be sure to cause an external resonator to oscillate. frequency control (1) middle-speed mode the internal clock is the frequency of x in divided by 8. at reset, this mode is selected. (2) high-speed mode the internal clock is the frequency of x in divided by 2. (3) low-speed mode the internal clock is the frequency of x cin divided by 2. a low-power consumption operation can be realized by stopping the main clock x in in this mode. to stop the main clock, set bit 5 of the cpu mode register to 1 . when the main clock x in is restarted, set enough time for oscillation to stabilize by programming. notes on clock generating circuit if you switch the mode between middle/high-speed and low-speed, stabilize both x in and x cin oscillations. the sufficient time is required for the sub clock to stabilize, especially immediately after power on and at returning from stop mode. when switching the mode between middle/high-speed and low-speed, set the frequency on condition that f(x in ) > 3 ? f(x cin ). oscillation control (1) stop mode if the stp instruction is executed, the internal clock stops at an h level, and x in and x cin oscillators stop. timer 1 is set to ff 16 and timer 2 is set to 01 16 . either x in divided by 16 or x cin divided by 16 is input to timer 1 as count source, and the output of timer 1 is connected to timer 2. the bits except bit 4 of the timer 123 mode register are cleared to 0. set the interrupt enable bits of timer 1 and timer 2 to disabled ( 0 ) before executing the stp instruction. oscillator restarts when an external interrupt is received, but the in- ternal clock is not supplied to the cpu until timer 2 underflows. this allows time for the clock circuit oscillation to stabilize. (2) wait mode if the wit instruction is executed, the internal clock stops at an h level. the states of x in and x cin are the same as the state before executing the wit instruction. the internal clock restarts at reset or when an interrupt is received. since the oscillator does not stop, normal operation can be started immediately after the clock is re- started. fig. 36 rc oscillation circuit fig. 37 resonator circuit c cin rf r d x c i n x c o u t o s c s e l x i n x o u t rosc x c i n x c o u t o s c s e lx i n x o u t c i n c out c c i n c c o u t r f r d 38 single-chip 8-bit cmos microcomputer mitsubishi microcomputers 38c8 group preliminar y notice: this is not a final specification. some parametric limits are subject to change. fig. 38 clock generating circuit block diagram w i t i n s t r u c t i o n stp i nstruct i on timing (internal clock) s r q stp i nstruct i on s r q m a i n c l oc k stop bi t s r q t i m e r 2 ti mer 1 1/2 1/4 x i n x out x c o u t x c i n i nterrupt request r e s e t ti mer 1 count source selection bit t i m e r 2 c o u n t s o u r c e s e l e c t i o n b i t l o w - s p e e d m o d e m i d d l e - / h i g h - s p e e d m o d e i n t e r n a l s y s t e m c l o c k s e l e c t i o n b i t ( n o t e ) m i d d l e - s p e e d m o d e hi g h -spee d mo d e or low-speed mode n o t e : w h e n s e l e c t i n g t h e x c o s c i l l a t i o n , s e t t h e p o r t x c s w i t c h b i t t o 1 . m a i n c l oc k di v i s i on rat i o se l ect i on bi t 0 1 1 0 1 0 i n t e r r u p t d i s a b l e f l a g i 1/2 1 0 39 single-chip 8-bit cmos microcomputer mitsubishi microcomputers 38c8 group preliminar y notice: this is not a final specification. some parametric limits are subject to change. fig. 39 state transitions of system clock l o w - s p e e d m o d e ( f ( ) = 1 6 k h z ) n otes 1 : s w i t c h t h e m o d e b y t h e a l l o w s s h o w n b e t w e e n t h e m o d e b l o c k s . ( d o n o t s w i t c h b e t w e e n t h e m o d e d i r e c t l y w i t h o u t a n a l l o w . ) 2 : t h e a l l m o d e s c a n b e s w i t c h e d t o t h e s t o p m o d e o r t h e w a i t m o d e a n d r e t u r n e d t o t h e s o u r c e m o d e w h e n t h e s t o p m o d e o r t h e w a i t m o d e i s e n d e d . 3 : t i m e r a n d l c d o p e r a t e i n t h e w a i t m o d e . 4 : w h e n t h e s t o p m o d e i s e n d e d , a d e l a y o f a p p r o x i m a t e l y 1 m s o c c u r s a u t o m a t i c a l l y b y t i m e r 1 a n d t i m e r 2 i n m i d d l e - / h i g h - s p e e d m o d e . 5 : w h e n t h e s t o p m o d e i s e n d e d , a d e l a y o f a p p r o x i m a t e l y 0 . 2 5 s o c c u r s a u t o m a t i c a l l y b y t i m e r 1 a n d t i m e r 2 i n l o w - s p e e d m o d e . 6 : w a i t u n t i l o s c i l l a t i o n s t a b i l i z e s a f t e r o s c i l l a t i n g t h e m a i n c l o c k x i n b e f o r e t h e s w i t c h i n g f r o m t h e l o w - s p e e d m o d e t o m i d d l e - / h i g h - s p e e d m o d e . 7 : t h e e x a m p l e a s s u m e s t h a t 4 m h z i s b e i n g a p p l i e d t o t h e x i n p i n a n d 3 2 k h z t o t h e x c i n p i n . i n d i c a t e s t h e i n t e r n a l c l o c k . c m 4 : s u b - c l o c k s t o p b i t 0 : s t o p p e d 1 : o s c i l l a t i n g c m 5 : m a i n c l o c k ( x i n C x o u t ) s t o p b i t 0 : o s c i l l a t i n g 1 : s t o p p e d c m 6 : m a i n c l o c k d i v i s i o n r a t i o s e l e c t i o n b i t 0 : f ( x i n ) / 2 ( h i g h - s p e e d m o d e ) 1 : f ( x i n ) / 8 ( m i d d l e - s p e e d m o d e ) c m 7 : i n t e r n a l s y s t e m c l o c k s e l e c t i o n b i t 0 : x i n C x o u t s e l e c t e d ( m i d d l e - / h i g h - s p e e d m o d e ) 1 : x c i n C x c o u t s e l e c t e d ( l o w - s p e e d m o d e ) cpu mo d e reg i ster (cpum : address 003b 16 ) b7 b4 r eset c m 6 0 1 c m 4 0 1 m i d d l e - s p e e d m o d e ( f ( ) = 0 . 5 m h z ) middle-speed mode (f( ) = 0.5 mhz) h i g h - s p e e d m o d e ( f ( ) = 2 m h z ) high-speed mode (f( ) = 2 mhz) low-speed mode (f( ) = 16 khz) low-speed mode (f( ) =16 khz) low-speed mode (f( ) =16 khz) cm 6 0 1 cm 6 0 1 c m 6 0 1 c m 4 0 1 c m 7 0 1 c m 7 0 1 c m 5 0 1 c m 5 0 1 c m 7 = 0 ( 4 m h z s e l e c t e d ) c m 6 = 1 ( m i d d l e - s p e e d ) c m 5 = 0 ( 4 m h z o s c i l l a t i n g ) c m 4 = 0 ( 3 2 k h z s t o p e d ) c m 7 = 0 ( 4 m h z s e l e c t e d ) c m 6 = 0 ( h i g h - s p e e d ) c m 5 = 0 ( 4 m h z o s c i l l a t i n g ) c m 4 = 0 ( 3 2 k h z s t o p e d ) cm 7 = 0 (4 mhz selected) cm 6 = 1 (middle-speed) cm 5 = 0 (4 mhz oscillating) cm 4 = 1 (32 khz oscillating) cm 7 = 0 (4 mhz selected) cm 6 = 0 (high-speed) cm 5 = 0 (4 mhz oscillating) cm 4 = 1 (32 khz oscillating) cm 7 = 1 (32 khz selected) cm 6 = 0 (high-speed) cm 5 = 0 (4 mhz oscillating) cm 4 = 1 (32 khz oscillating) cm 7 = 1 (32 khz selected) cm 6 = 1 (middle-speed) cm 5 = 0 (4 mhz oscillating) cm 4 = 1 (32 khz oscillating) c m 7 = 1 ( 3 2 k h z s e l e c t e d ) c m 6 = 1 ( m i d d l e - s p e e d ) c m 5 = 1 ( 4 m h z s t o p p e d ) c m 4 = 1 ( 3 2 k h z o s c i l l a t i n g ) c m 7 = 1 ( 3 2 k h z s e l e c t e d ) c m 6 = 0 ( h i g h - s p e e d ) c m 5 = 1 ( 4 m h z s t o p p e d ) c m 4 = 1 ( 3 2 k h z o s c i l l a t i n g ) c m 4 0 1 c m 6 0 1 c m 5 0 1 c m 6 0 1 c m 6 0 1 c m 4 1 0 c m 6 0 1 c m 5 1 0 40 single-chip 8-bit cmos microcomputer mitsubishi microcomputers 38c8 group preliminar y notice: this is not a final specification. some parametric limits are subject to change. notes on programming processor status register the contents of the processor status register (ps) after a reset are undefined, except for the interrupt disable flag (i) which is 1. after a reset, initialize flags which affect program execution. in particular, it is essential to initialize the index x mode (t) and the decimal mode (d) flags because of their effect on calculations. interrupts the contents of the interrupt request bits do not change immediately after they have been written. after writing to an interrupt request reg- ister, execute at least one instruction before performing a bbc or bbs instruction. decimal calculations ? to calculate in decimal notation, set the decimal mode flag (d) to 1, then execute an adc or sbc instruction. after executing an adc or sbc instruction, execute at least one instruction before executing a sec, clc, or cld instruction. ? in decimal mode, the values of the negative (n), overflow (v), and zero (z) flags are invalid. timers if a value n (between 0 and 255) is written to a timer latch, the fre- quency division ratio is 1/(n+1). multiplication and division instructions ? the index x mode (t) and the decimal mode (d) flags do not affect the mul and div instruction. ? the execution of these instructions does not change the contents of the processor status register. ports the contents of the port direction registers cannot be read. the fol- lowing cannot be used: ? the data transfer instruction (lda, etc.) ? the operation instruction when the index x mode flag (t) is 1 ? the addressing mode which uses the value of a direction register as an index ? the bit-test instruction (bbc or bbs, etc.) to a direction register ? the read-modify-write instructions (ror, clb, or seb, etc.) to a direction register. use instructions such as ldm and sta, etc., to set the port direction registers. serial i/o in clock synchronous serial i/o, if the receive side is using an exter- nal clock and it is to output the s rdy signal, set the transmit enable bit, the receive enable bit, and the s rdy output enable bit to 1 . serial i/o continues to output the final bit from the txd pin after trans- mission is completed. a-d converter the comparator is constructed linked to a capacitor. when the con- version speed is not enough, the conversion accuracy might be ru- ined by the disappearance of the charge. when a-d conversion is performed in the middle-speed mode or the high-speed mode, set f(x in ) to at least 500 khz. do not execute the stp or wit instruction during an a-d conversion because a normal conversion result is not obtained. instruction execution time the instruction execution time is obtained by multiplying the frequency of the internal clock by the number of cycles needed to execute an instruction. the number of cycles required to execute an instruction is shown in the list of machine instructions. the frequency of the internal clock is half of the x in frequency. at stp instruction release at the stp instruction release, all bits of the timer 12 mode register are cleared. lcd control when using the voltage multiplier, apply prescribed voltage to the v lin pin in the state in which the lcd enable bit is 0 , and set the voltage multiplier enable bit to 1 . 41 single-chip 8-bit cmos microcomputer mitsubishi microcomputers 38c8 group preliminar y notice: this is not a final specification. some parametric limits are subject to change. data required for mask orders the following are necessary when ordering a mask rom produc- tion: 1. mask rom order confirmation form ? 1 2. mark specification form ? 2 3. data to be written to rom, in eprom form (three identical copies) or one floppy disk. for the mask rom confirmation and the mark specifications, refer to the mitsubishi mcu technical information homepage. ? 1 mask rom confirmation forms http://www.infomicom.mesc.co.jp/38000/38ordere.htm ? 2 mark specification forms http://www.infomicom.mesc.co.jp/mela/markform.htm rom programming method the built-in prom of the blank one time prom version and built-in eprom version can be read or programmed with a general-purpose prom programmer using a special programming adapter (pca7447fp). the prom of the blank one time prom version is not tested or screened in the assembly process and following processes. to en- sure proper operation after programming, the procedure shown in figure 40 is recommended to verify programming. fig. 40 programming and testing of one time prom version programming with prom programmer screening (caution) (150 c for 40 hours) verification with prom programmer functional check in target device the screening temperature is far highe r than the storage temperature. neve r expose to 150 c exceeding 100 hours. caution : 42 single-chip 8-bit cmos microcomputer mitsubishi microcomputers 38c8 group preliminar y notice: this is not a final specification. some parametric limits are subject to change. parameter power source voltage input voltage p0 0 C p0 7 , p1 0 C p1 7 , p2 0 C p2 7, p3 0 C p3 3, p4 0 C p4 7 input voltage c 1 , c 2 input voltage reset, x in , x cin input voltage v lin input voltage v l1 , v l2 , v l3 , v l4 , v l5 output voltage p0 0 C p0 7 , p1 0 C p1 7 , p2 0 C p2 7 , p3 0 C p3 3, p4 1 C p4 7 output voltage c 1 , c 2 , c 3 output voltage com 0 C com 31 , seg 0 C seg 67 output voltage x out , x cout power dissipation operating temperature storage temperature symbol v cc v i v i v i v i v i v o v o v o v o p d t opr t stg electrical characteristics table 10 absolute maximum ratings conditions ratings C 0.3 to 7.0 C 0.3 to v cc +0.3 C 0.3 to 7.0 C 0.3 to v cc +0.3 C 0.3 to 7.0 C 0.3 to 7.0 C 0.3 to v cc +0.3 C 0.3 to 7.0 C 0.3 to v l5 +0.3 C 0.3 to v cc +0.3 300 C 20 to 85 C 40 to 125 unit v v v v v v v v v v mw c c all voltages are based on vss. output transistors are cut off. when voltage multiplier is not operated. v l1 v l2 v l3 v l4 v l5 ta = 25 c table 11 recommended operating conditions (vcc = 2.2 to 5.5 v, ta = C 20 to 85 c, unless otherwise noted) power source high-speed mode f(x in ) 8 mhz voltage high-speed mode f(x in ) 4 mhz middle-speed mode f(x in ) 8 mhz middle-speed mode (mask rom version) f(x in ) 4 mhz middle-speed mode (one time prom version) f(x in ) 4 mhz low-speed mode (mask rom version) low-speed mode (one time prom version) power source voltage power source voltage v lin power source voltage v l5 analog input voltage an 0 C an 7 h input voltage p0 0 C p0 7 , p1 0 C p1 7 , p4 0 , p4 3 , p4 5 , p4 7 h input voltage p2 0 C p2 7 , p3 0 C p3 3 , p4 1 , p4 2 , p4 4 , p4 6 h input voltage reset h input voltage x in l input voltage p0 0 C p0 7 , p1 0 C p1 7 , p4 0 , p4 3 , p4 5 , p4 7 l input voltage p2 0 C p2 7 , p3 0 C p3 3 , p4 1 , p4 2 , p4 4 , p4 6 l input voltage reset l input voltage x in h total peak output current all ports (note 1) l total peak output current all ports (note 1) h total average output current all ports (note 2) l total average output current all ports (note 2) h peak output current all ports (note 3) l peak output current all ports (note 3) h average output current all ports (note 4) l average output current all ports (note 4) oscillation resistor at selecting rc oscillation v cc v ss v lin v l5 v ia v ih v ih v ih v ih v il v il v il v il i oh(peak) i ol(peak) i oh(avg) i ol(avg) i oh(peak) i ol(peak) i oh(avg) i ol(avg) r osc limits v v v v v v v v v v v v v v v v v v v ma ma ma ma ma ma ma ma k ? parameter min. 4.0 3.0 2.7 2.2 2.5 2.2 2.5 v ss 0.7v cc 0.8v cc 0.8v cc 0.8v cc v ss v ss v ss v ss 5 typ. 5.0 5.0 5.0 5.0 5.0 5.0 5.0 0 8.2 max. 5.5 5.5 5.5 5.5 5.5 5.5 5.5 2.33 7.0 v cc v cc v cc v cc v cc 0.3v cc 0.2v cc 0.2v cc 0.2v cc C 60.0 60.0 C 30.0 30.0 C 5.0 10.0 C 2.5 5.0 10 symbol unit notes 1: the total peak output current is the peak value of the peak currents flowing through all the applicable ports. 2: the total average output current is the average value measured over 100 ms flowing through all the applicable ports. 3: the peak output current is the peak current flowing in each port. 4: the average output current is an average value measured over 100 ms. 43 single-chip 8-bit cmos microcomputer mitsubishi microcomputers 38c8 group preliminar y notice: this is not a final specification. some parametric limits are subject to change. table 12 recommended operating conditions (mask rom version) (vcc = 2.2 to 5.5 v, ta = C 20 to 85 c, unless otherwise noted) timer x, timer y input frequency (duty cycle 50%) main clock input oscillation frequency (note 1) sub-clock input oscillation frequency (notes 1, 2) f(cntr 0 ) f(cntr 1 ) f(x in ) f(x cin ) limits mhz mhz mhz mhz khz parameter min. typ. 32.768 max. f(x in )/2 8.0 (20 ? v cc C 8)/13 8.0 50 symbol unit high-speed mode (4.0 v v cc 5.5 v) high-speed mode (2.2 v v cc < 4.0 v) middle-speed mode (2.7 v v cc 5.5 v) notes 1: when the oscillation frequency has a duty cycle of 50 %. 2: when using the microcomputer in low-speed mode, set the sub-clock input oscillation frequency on condition that f(x cin ) < f(x in )/3. table 13 recommended operating conditions (prom version) (vcc = 2.5 to 5.5 v, ta = C 20 to 85 c, unless otherwise noted) timer x, timer y input frequency (duty cycle 50%) main clock input oscillation frequency (note 1) sub-clock input oscillation frequency (notes 1, 2) f(cntr 0 ) f(cntr 1 ) f(x in ) f(x cin ) limits mhz mhz mhz mhz khz parameter min. typ. 32.768 max. f(x in )/2 8.0 4 ? v cc C 8 8.0 50 symbol unit high-speed mode (4.0 v v cc 5.5 v) high-speed mode (2.5 v v cc < 4.0 v) middle-speed mode (2.7 v v cc 5.5 v) notes 1: when the oscillation frequency has a duty cycle of 50 %. 2: when using the microcomputer in low-speed mode, set the sub-clock input oscillation frequency on condition that f(x cin ) < f(x in )/3. conditions conditions 44 single-chip 8-bit cmos microcomputer mitsubishi microcomputers 38c8 group preliminar y notice: this is not a final specification. some parametric limits are subject to change. i oh = C 5.0 ma v cc = 5.0 v i oh = C 1.5 ma v cc = 5.0 v i oh = C 1.25 ma v cc = 2.2 v i oh = C 5.0 ma v cc = 5.0 v i oh = C 1.5 ma v cc = 5.0 v i oh = C 1.25 ma v cc = 2.2 v i ol = 5.0 ma v cc = 5.0 v i ol = 1.5 ma v cc = 5.0 v i ol = 1.25 ma v cc = 2.2 v i ol = 5.0 ma v cc = 5.0 v i ol = 1.5 ma v cc = 5.0 v i ol = 1.25 ma v cc = 2.2 v v i = v ss pull-ups off v cc = 5.0 v, v i = v cc pull-ups on v cc = 2.2 v, v i = v cc pull-ups on v i = v ss v i = v ss h output voltage p0 0 C p0 7 , p1 0 C p1 7 , p3 0 C p3 3 h output voltage p2 0 C p2 7 , p4 1 C p4 7 l output voltage p0 0 C p0 7 , p1 0 C p1 7 , p3 0 C p3 3 l output voltage p2 0 C p2 7 , p4 1 C p4 7 hysteresis int 0 , int 1 , adt, cntr 0 , cntr 1 , p2 0 C p2 7 hysteresis s clk , rxd hysteresis reset h input current all ports h input current reset h input current x in l input current all ports l input current reset l input current x in limits v v v v v v v v v v v v v v v a a a a a a a a parameter min. v cc C 2.0 v cc C 0.5 v cc C 1.0 v cc C 2.0 v cc C 0.5 v cc C 1.0 C 60.0 C 5.0 typ. 0.5 0.5 0.5 4.0 C 120.0 C 20.0 C 4.0 max. 2.0 0.5 1.0 2.0 0.5 1.0 5.0 5.0 C 5.0 C 240.0 C 40.0 C 5.0 symbol unit test conditions v oh v oh v ol v ol v t+ C v t- v t+ C v t- v t+ C v t- i ih i ih i ih i il i il i il table 14 electrical characteristics (vcc = 2.2 to 5.5 v, ta = C 20 to 85 c, unless otherwise noted) 45 single-chip 8-bit cmos microcomputer mitsubishi microcomputers 38c8 group preliminar y notice: this is not a final specification. some parametric limits are subject to change. ram hold voltage power source current a-d converter current dissipation v l5 input current (note) rc oscillation frequency limits parameter min. 2.0 1.5 typ. 5.0 5.5 3.0 1.0 20.0 0.9 0.3 4.5 0.1 0.8 3 2.5 max. 5.5 11.0 6.0 2.0 40.0 1.8 0.6 9.0 1.0 10.0 1.6 6 3.5 symbol unit when clock is stopped high-speed mode, vcc = 5.0 v f(x in ) = 8.0 mhz f(x cin ) = 32.768 khz middle-speed mode, vcc = 5.0 v f(x in ) = 8.0 mhz f(x cin ) = 32.768 khz middle-speed mode, vcc = 3.0 v f(x in ) = 8.0 mhz f(x cin ) = 32.768 khz low-speed mode, v cc = 3.0 v, f(x in ) = stopped f(x cin ) = 32.768 khz high-/middle-speed mode, v cc = 5.0 v, f(x in ) = 8.0 mhz (in wit state) f(x cin ) = 32.768 khz middle-speed mode, vcc = 3.0 v f(x in ) = 8.0 mhz (in wit state) f(x cin ) = 32.768 khz low-speed mode, v cc = 3.0 v, f(x in ) = stopped f(x cin ) = 32.768 khz (in wit state) all oscillation stopped ta = 25 c, output transistors off (in stp state) all oscillation stopped ta = 85 c, output transistors off (in stp state) current increase at a-d converter operated, f(x in ) = 8.0 mhz v l5 = 6.0 v, ta = 25 c r osc = 8.2 k ? test conditions v ram i cc i ad i l5 f rosc v ma ma ma a ma ma a a a ma a mhz table 15 electrical characteristics (vcc = 2.2 to 5.5 v, ta = C 20 to 85 c, unless otherwise noted) note: when normal drivability (drivability selection bit 1 = 0 , drivability selection bit 2 = 0 ) is selected. 46 single-chip 8-bit cmos microcomputer mitsubishi microcomputers 38c8 group preliminar y notice: this is not a final specification. some parametric limits are subject to change. resolution absolute accuracy (excluding quantization error) conversion time analog port input current unit bits lsb lsb s a limits parameter min. 30.5 typ. 0.5 max. 10 4 6 34 5.0 symbol v cc = 2.7 C 5.5 v v cc = 2.5 C 2.7 v (ta = C 10 to 50 c) f(x in ) = 4 mhz (note) test conditions t conv i ia table 16 a-d converter characteristics (vcc = 2.2 to 5.5 v, vss = 0 v, ta = C 20 to 85 c, f(x in ) 4 mhz, in middle-speed/high-speed mode) note: when main clock is selected as system clock. t w (reset) t c (x in ) t wh (x in ) t wl (x in ) t c (cntr) t wh (cntr) t wl (cntr) t wh (int) t wl (int) t c (s clk ) t wh (s clk ) t wl (s clk ) t su (rxd-s clk ) t h (s clk -rxd) reset input l pulse width main clock input cycle time (x in input) main clock input h pulse width main clock input l pulse width cntr 0 , cntr 1 input cycle time cntr 0 , cntr 1 input h pulse width cntr 0 , cntr 1 input l pulse width int 0 , int 1 input h pulse width int 0 , int 1 input l pulse width serial i/o clock input cycle time (note) serial i/o clock input h pulse width (note) serial i/o clock input l pulse width (note) serial i/o input setup time serial i/o input hold time t w (reset) t c (x in ) t wh (x in ) t wl (x in ) t c (cntr) t wh (cntr) t wl (cntr) t wh (int) t wl (int) t c (s clk ) t wh (s clk ) t wl (s clk ) t su (rxd-s clk ) t h (s clk -rxd) limits s ns ns ns ns ns ns ns ns ns ns ns ns ns parameter min. 2 125 45 40 250 105 105 80 80 800 370 370 220 100 typ. max. symbol unit limits s ns ns ns ns ns ns ns ns ns ns ns ns ns parameter min. 2 125 45 40 900/(v cc C 0.4) tc(cntr)/2 C 20 tc(cntr)/2 C 20 230 230 2000 950 950 400 200 typ. max. symbol unit table 17 timing requirements 1 (vcc = 4.0 to 5.5 v, vss = 0 v, ta = C 20 to 85 c, unless otherwise noted) reset input l pulse width main clock input cycle time (x in input) main clock input h pulse width main clock input l pulse width cntr 0 , cntr 1 input cycle time cntr 0 , cntr 1 input h pulse width cntr 0 , cntr 1 input l pulse width nt 0 , int 1 input h pulse width nt 0 , int 1 input l pulse width serial i/o clock input cycle time (note) serial i/o clock input h pulse width (note) serial i/o clock input l pulse width (note) serial i/o input setup time serial i/o input hold time table 18 timing requirements 2 (vcc = 2.2 to 4.0 v, vss = 0 v, ta = C 20 to 85 c, unless otherwise noted) note: when bit 6 of address 001a 16 is 1 . divide this value by four when bit 6 of address 001a 16 is 0 . note: when bit 6 of address 001a 16 is 1 . divide this value by four when bit 6 of address 001a 16 is 0 . 47 single-chip 8-bit cmos microcomputer mitsubishi microcomputers 38c8 group preliminar y notice: this is not a final specification. some parametric limits are subject to change. t wh (s clk ) t wl (s clk ) t d (s clk -txd) t v (s clk -txd) t r (s clk ) t f (s clk ) t r (cmos) t f (cmos) t wh (s clk ) t wl (s clk ) t d (s clk -txd) t v (s clk -txd) t r (s clk ) t f (s clk ) t r (cmos) t f (cmos) limits parameter min. t c (s clk )/2 C 30 t c (s clk )/2 C 30 C 30 typ. 10 10 max. 140 30 30 30 30 symbol unit ns ns ns ns ns ns ns ns notes 1: when the p4 5 /txd p-channel output disable bit of the uart control register (bit 4 of address 001b 16 ) is 0 . 2: the x out and x cout pins are excluded. serial i/o clock output h pulse width serial i/o clock output l pulse width serial i/o output delay time (note 1) serial i/o output valid time (note 1) serial i/o clock output rising time serial i/o clock output falling time cmos output rising time (note 2) cmos output falling time (note 2) table 19 switching characteristics 1 (vcc = 4.0 to 5.5 v, vss = 0 v, ta = C 20 to 85 c, unless otherwise noted) limits ns ns ns ns ns ns ns ns parameter min. t c (s clk )/2 C 50 t c (s clk )/2 C 50 C 30 typ. 20 20 max. 350 50 50 50 50 symbol unit serial i/o clock output h pulse width serial i/o clock output l pulse width serial i/o output delay time (note 1) serial i/o output valid time (note 1) serial i/o clock output rising time serial i/o clock output falling time cmos output rising time (note 2) cmos output falling time (note 2) table 20 switching characteristics 2 (vcc = 2.2 to 4.0 v, vss = 0 v, ta = C 20 to 85 c, unless otherwise noted) notes 1: when the p4 5 /txd p-channel output disable bit of the uart control register (bit 4 of address 001b 16 ) is 0 . 2: the x out and x cout pins are excluded. fig. 41 circuit for measuring output switching characteristics m e a s u r e m e n t o u t p u t p i n 1 0 0 p f c m o s o u t p u t n o t e : w h e n b i t 4 o f t h e u a r t c o n t r o l r e g i s t e r ( a d d r e s s 0 0 1 b 1 6 ) i s 1 . ( n - c h a n n e l o p e n - d r a i n o u t p u t m o d e ) n - c h a n n e l o p e n - d r a i n o u t p u t ( n o t e ) 1 k ? 100 p f m e a s u r e m e n t o u t p u t p i n 48 single-chip 8-bit cmos microcomputer mitsubishi microcomputers 38c8 group preliminar y notice: this is not a final specification. some parametric limits are subject to change. fig. 42 timing diagram 0 . 2 v c c t d ( s c l k - t x d ) t f 0 . 2 v c c 0 . 8 v c c 0 . 8 v c c t r t s u ( r x d - s c l k )t h ( s c l k - r x d ) t v ( s c l k - t x d ) t c ( s c l k ) t w l ( s c l k ) t w h ( s c l k ) t x d r x d s c l k 0 . 2 v c c t w l ( x i n ) 0 . 8 v c c t w h ( x i n ) t c ( x i n ) x i n 0 . 2 v c c 0 . 8 v c c t w ( r e s e t ) r e s e t 0 . 2 v c c t w l ( c n t r ) 0 . 8 v c c t w h ( c n t r ) t c ( c n t r ) 0 . 2 v c c t w l ( i n t ) 0 . 8 v c c t w h ( i n t ) c n t r 0 , c n t r 1 i n t 0, i n t 1 49 single-chip 8-bit cmos microcomputer mitsubishi microcomputers 38c8 group preliminar y notice: this is not a final specification. some parametric limits are subject to change. package outline lqfp144-p-2020-0.50 weight(g) e 1.23 jedec code eiaj package code lead material cu alloy 144p6q-a plastic 144pin 20 ? ? 2001 mitsubishi electric corp. first publication, effective jan. 2001. specifications subject to change without notice. notes regarding these materials ? these materials are intended as a reference to assist our customers in the selection of the mitsubishi semiconductor product b est suited to the customers application; they do not convey any license under any intellectual property rights, or any other rights, belonging to mitsubishi electric corporation or a third party. ? mitsubishi electric corporation assumes no responsibility for any damage, or infringement of any third-partys rights, origina ting in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. ? all information contained in these materials, including product data, diagrams, charts, programs and algorithms represents inf ormation on products at the time of publication of these materials, and are subject to change by mitsubishi electric corporation without notice due to product improvements or other reasons. it is therefore recommended that c ustomers contact mitsubishi electric corporation or an authorized mitsubishi semiconductor product distributor for the latest product information before purchasing a product listed herein. the information described here may contain technical inaccuracies or typographical errors. mitsubishi electric corporation assu mes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. please also pay attention to information published by mitsubishi electric corporation by various means, including the mitsubish i semiconductor home page (http://www.mitsubishichips.com). ? when using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. mitsubishi electric corporation assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. ? mitsubishi electric corporation semiconductors are not designed or manufactured for use in a device or system that is used und er circumstances in which human life is potentially at stake. please contact mitsubishi electric corporation or an authorized mitsubishi semiconductor product distributor when considering the use of a product contained herei n for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. ? the prior written approval of mitsubishi electric corporation is necessary to reprint or reproduce in whole or in part these m aterials. ? if these products or technologies are subject to the japanese export control restrictions, they must be exported under a licen se from the japanese government and cannot be imported into a country other than the approved destination. any diversion or reexport contrary to the export control laws and regulations of japan and/or the country of destination is pro hibited. ? please contact mitsubishi electric corporation or an authorized mitsubishi semiconductor product distributor for further detai ls on these materials or the products contained therein. keep safety first in your circuit designs! ? mitsubishi electric corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. trouble with semiconductors may lead to personal injury, fire or property damage. remember to give due consideration to safety when making your circuit designs, with a ppropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of non-flammable material or (iii) prevention against any malfunction or mishap. head office: 2-2-3, marunouchi, chiyoda-ku, tokyo 100-8310, japan revision history 38c8 group data sheet rev. date description page summary (1/1) 1.0 01/18/01 first edition |
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